Four-dimensional address topology for circuits with stacked multilayer crossbar arrays

Abstract

We present a topological framework that provides a simple yet powerful electronic circuit architecture for constructing and using multilayer crossbar arrays, allowing a significantly increased integration density of memristive crosspoint devices beyond the scaling limits of lateral feature sizes. The truly remarkable feature of such circuits, which is an extension of the CMOL (Cmos + MOLecular-scale devices) concept for an area-like interface to a three-dimensional system, is that a large-feature-size complimentary metal-oxide-semiconductor (CMOS) substrate can provide high-density interconnects to multiple crossbar layers through a single set of vertical vias. The physical locations of the memristive devices are mapped to a four-dimensional logical address space such that unique access from the CMOS substrate is provided to every device in a stacked array of crossbars. This hybrid architecture is compatible with digital memories, field-programmable gate arrays, and biologically inspired adaptive networks and with state-of-the-art integrated circuit foundries.

Fig. 1.

Typical structures for (A) arrays with each cell having a dedicated access element (transistor) and (B) crossbar arrays with equivalent circuit representations used in the following discussion. The specific case n = 3 is used for illustration, but practical arrays are much larger (e.g., to reduce peripheral overhead in memory applications).

Fig. 2.

Two-dimensional circuits with an area distributed interface. (A) Top view of the crossbar structure showing α for r = 3. (B) Cut-away illustration showing the two types of vias connecting the CMOS control circuitry to the lower (blue) and upper (red) wire levels of the crossbar. (C, D) Corresponding equivalent circuit diagram for the n = 5 primitive cell array using the notations from Fig. 1.

Fig. 3.

Three-dimensional hybrid CMOS/crossbar circuit with an area distributed interface. (A) Cut-away illustration of the circuit showing four crossbar layers (M = 4), (B) equivalent circuit diagram of the virtual crossbar array for the case N = 5, M = 2, and r = 3, and (C–E) examples of the connection pattern between two layers. Light blue circles are guides for the eye highlighting the specific via used for the explanation in the text. In C, the cells forming a connectivity domain and the corresponding wires are highlighted with gray and yellow colors. Similarly, D highlights the wires implementing the translation of red vias within the considered domain, whereas E shows the corresponding connectivity domains of a given blue via for the first and second layers.

Fig. 4.

Cross-section of three-dimensional circuit illustrating (A) “ideal” alignment between layers and (B) more realistic scenario with overlay error.