Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits

Abstract

Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

Fig. 1.

The 3D CMOS circuit and vertical interconnection. (A) Schematic of a two-layer CMOS inverter circuit. Layer-1 and layer-2 are constructed with complementary n-type InAs NWs and p-type Ge/Si core/shell NWs, and vertical interconnections are achieved at the two gate electrodes (input) and the two drain electrodes (output). GND denotes electrical ground. (B) Optical microscope image of vertically interconnected CMOS inverter. Red dashed box indicates via interconnection at the input of CMOS inverter. (C) Side tilted-view schematic drawing (rotated 90° counterclockwise of red dashed box in B) of via interconnection at the input of CMOS inverter. (D) Tilted-view SEM image (rotated 90° counterclockwise of red dashed box in B) of via interconnection at the input of CMOS inverter. (Scale bar: 5 μm.)

Fig. 2.

Vertically interconnected CMOS inverter. (A) Optical microscope image of isolated n-InAs and p-Ge/Si NW FETs (left column), and two-layer interconnected CMOS inverters (right column). The n-InAs NW FETs were fabricated in layer-1 (light-blue contrast and arrow), and the p-Ge/Si NW FETs were fabricated in layer-2 (light-brown contrast and arrow). (B) I vs. V_g characteristics data recorded from representative InAs layer-1 and Ge/Si layer-2 NW devices with |V_ds| = 1 V. The data from the InAs NW FET were recorded before fabrication of the layer-2. (C) V_out vs. V_in (black curve) and gain = dV_out/dV_in vs. V_in (red curve) for a CMOS inverter at supply voltage, V_DD, of 4 V. (Inset) Circuit diagram for the vertically interconnected two-layer CMOS inverter.

Fig. 3.

Vertically integrated CMOS ring oscillator. (A) Optical micrograph and circuit diagram of two-layer, vertically interconnected three-stage CMOS ring oscillator. The layer-1 n-InAs and layer-2 p-Ge/Si NW FETs exhibit light-blue and brown contrast in the image. (B) Amplitude vs. time response recorded at via position by using a high-impedance probe (see Materials and Methods). The supply voltage, V_DD, is 8 V, and the self-sustained oscillation frequency is 108 MHz. (C) Oscillation frequency (black curve) and output voltage swing (red curve) vs. supply voltage (V_DD) characteristics of the vertically interconnected three-stage CMOS ring oscillator.