Top-gated graphene nanoribbon transistors with ultrathin high-k dielectrics

Abstract

The integration ultrathin high dielectric constant (high-k) materials with graphene nanoribbons (GNRs) for top-gated transistors can push their performance limit for nanoscale electronics. Here we report the assembly of Si/HfO(2) core/shell nanowires on top of individual GNRs as the top-gates for GNR field-effect transistors with ultrathin high-k dielectrics. The Si/HfO(2) core/shell nanowires are synthesized by atomic layer deposition of the HfO(2) shell on highly doped silicon nanowires with a precise control of the dielectric thickness down to 1-2 nm. Using the core/shell nanowires as the top-gates, high-performance GNR transistors have been achieved with transconductance reaching 3.2 mS microm(-1), the highest value for GNR transistors reported to date. This method, for the first time, demonstrates the effective integration of ultrathin high-k dielectrics with graphene with precisely controlled thickness and quality, representing an important step toward high-performance graphene electronics.

Fig. 1

Schematic illustration of the fabrication process to obtain top-gated graphene transistors using Si/HfO₂ coreshell nanowires as the etching mask and top-gate. (a) and (e), An Si/HfO₂ coreshell nanowire is aligned on top of graphene using a dry-transfer process, and the source-drain electrodes are fabricated by electron-beam lithography. (b) and (f), Oxygen plasma etch is used to remove the unprotected graphene, leaving only the GNR underneath the nanowire connected to two large graphene blocks underneath the source and drain electrodes. (c) and (g), The top-half of the HfO₂ shell was etched away using argon plasma to expose the silicon core gate for contact to external electrode. (d) and (h), The top gate electrode is defined through lithography and metallization process.

Fig. 2

TEM characterization of Si/HfO₂ coreshell nanowires. (a) Schematic illustration of the synthesis of Si/HfO₂ coreshell nanowires. Highly doped p-type silicon nanowire arrays were synthesized using catalytic chemical vapour deposition. Atomic layer deposition was used to grow HfO₂ shell with controlled thickness. (b) TEM and (c) HRTEM images of Si/HfO₂ coreshell nanowires.

Fig. 3

Characterization of the graphene/HfO₂ interface. (a) A SEM image of a typical device. (b) A cross-section TEM image of the top gate stack. (c) A cross-section HRTEM image of the interface between nanowires and a multi-layers graphene, which indicate that the graphene layers are intimately integrated with the Si/HfO₂ nanowire without any obvious gap or impurities between them. A TEM image of multi-layer graphene device is shown here because it is very difficult to visualize the mono- or few-layer of graphene nanoribbon under the nanowire due to significant electron-beam damage while conducting TEM studies.

Fig. 4

Room temperature electrical properties of the top-gated GNR device by using Si/HfO₂ coreshell nanowire as the top-gate. (a) Gate leakage current versus top-gate voltage. The leakage current is negligible within ± 1 V range. (b) I_ds-V_ds output characteristics at variable top-gate voltage starting from 0.6 V at bottom to −1.0 V at top in the step of −0.2 V. (c) The transfer characteristics I_ds-V_TG at V_ds = 0.10 and 1.0 V. (d) I_ds-V_TG and I_ds-V_BG transfer characteristics at V_ds = 1 V. (e) Transconductance as a function of top-gate voltage V_TG and back gate voltage V_BG (inset). (f) Two-dimensional plot of the device conductance at varying V_BG and V_TG bias, the unit in the colour scale is μS.