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. 2010 May 4;22(17):1941-5.
doi: 10.1002/adma.200904415.

High-performance top-gated graphene-nanoribbon transistors using zirconium oxide nanowires as high-dielectric-constant gate dielectrics

Lei Liao  1 , Jingwei Bai, Yung-Chen Lin, Yongquan Qu, Yu Huang, Xiangfeng Duan
Affiliations

High-performance top-gated graphene-nanoribbon transistors using zirconium oxide nanowires as high-dielectric-constant gate dielectrics

Lei Liao et al. Adv Mater. .
No abstract available

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Figures

Figure 1
Figure 1
Schematic illustration of the fabrication process to obtain top-gated graphene transistors using dielectric oxide nanowires as the etching mask and top-gate dielectric. a) A dielectric nanowire is aligned on top of graphene using a dry-transfer process without any additional chemical functionalization to minimize the possibility to introduce defects/impurities into the graphene-dielectric interface, and the source-drain electrodes are fabricated by electron-beam lithography. b) Oxygen plasma etch is used to remove the unprotected graphene, leaving only the GNR underneath the dielectric nanowires connected to two large graphene blocks underneath the source and drain electrodes. c) The top gate electrode is defined through lithography and metallization process.
Figure 2
Figure 2
Characterization of ZrO2 nanowires and top-gated GNR transistors with ZrO2 nanowires as the gate dielectric. a) An SEM image of ZrO2 nanowires. b) A TEM image of a ZrO2 nanowire, and the inset shows the SAED pattern of a ZrO2 nanowire. c) The EDX spectrum of ZrO2 nanowires shows only zirconium and oxygen signals. The carbon signal comes from the carbon membrane on TEM grid. d) The SEM image of a top-gated GNR transistor with ZrO2 nanowire as top-gate dielectric. The gate length is about 500 nm and the diameter of the nanowire is 50 nm. Inset shows an AFM image of a ~15 nm wide GNR obtained under ZrO2 nanowire after oxygen plasma etching. The scale bar indicates 200 nm. e) Gate leak current versus top-gate voltage. The leak current is negligible within Vgs ±2 V. f) Ids-Vds output characteristics at variable top gate voltage starting from 0.4 V at bottom to −1.0 V at top in the step of −0.2 V. g) The transfer characteristics Ids-VTG at various Vds = 0.01, 0.10 and 1.0 V. h) Ids-VTG (red curve) and Ids-VBG (black curve) transfer characteristics at Vds = 1 V. i) Transconductance gm as a function of top-gate voltage VTG and back gate voltage VBG (inset).
Figure 3
Figure 3
Independently addressable GNR device array. a) An SEM image of two independently addressable top-gated GNR FETs. b) Transfer characteristics of two top-gated GNR FETs at Vds = 0.1 V. c) The SEM image of a logic OR gates built from GNR transistors. The inset shows the schematic circuit diagram. d) The OR gate output characteristics with double top-gates. The operating voltage is Vdd = 1V. The inputs for the two gates, A and B, are 1V for state 1 and 0 for state 0.
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