High-speed graphene transistors with a self-aligned nanowire gate

Abstract

Graphene has attracted considerable interest as a potential new electronic material. With its high carrier mobility, graphene is of particular interest for ultrahigh-speed radio-frequency electronics. However, conventional device fabrication processes cannot readily be applied to produce high-speed graphene transistors because they often introduce significant defects into the monolayer of carbon lattices and severely degrade the device performance. Here we report an approach to the fabrication of high-speed graphene transistors with a self-aligned nanowire gate to prevent such degradation. A Co(2)Si-Al(2)O(3) core-shell nanowire is used as the gate, with the source and drain electrodes defined through a self-alignment process and the channel length defined by the nanowire diameter. The physical assembly of the nanowire gate preserves the high carrier mobility in graphene, and the self-alignment process ensures that the edges of the source, drain and gate electrodes are automatically and precisely positioned so that no overlapping or significant gaps exist between these electrodes, thus minimizing access resistance. It therefore allows for transistor performance not previously possible. Graphene transistors with a channel length as low as 140 nm have been fabricated with the highest scaled on-current (3.32 mA μm(-1)) and transconductance (1.27 mS μm(-1)) reported so far. Significantly, on-chip microwave measurements demonstrate that the self-aligned devices have a high intrinsic cut-off (transit) frequency of f(T) = 100-300 GHz, with the extrinsic f(T) (in the range of a few gigahertz) largely limited by parasitic pad capacitance. The reported intrinsic f(T) of the graphene transistors is comparable to that of the very best high-electron-mobility transistors with similar gate lengths.

Figure 1. Schematic illustration of a high-speed graphene transistor with a Co₂Si/Al₂O₃ core/shell nanowire as the self-aligned top-gate

a, Schematic illustration of the three-dimensional view of the device layout. b, Schematic illustration of the cross-sectional view of the device. In this device, the Co₂Si/Al₂O₃ core/shell nanowire defines the channel length, with the 5 nm Al₂O₃ shell in functioning as the gate dielectrics, and the metallic Co₂Si core functioning as the self-integrated local gate, and the self-aligned Pt thin film pads as the source and drain electrodes

Figure 2. Characterization of Co₂Si and Co₂Si/Al₂O₃ core/shell nanowires

a, SEM image of the Co₂Si nanowires. The nanowires were synthesized through a chemical vapour deposition process with the diameters typically in the range of 100–300 nm and the lengths around 10 μm. b, TEM image of a Co₂Si/Al₂O₃ core/shell nanowire shows a uniform coating of the amorphous Al₂O₃ (light contrast) surrounding the single-crystal Co₂Si core (dark contrast). c, The I–V characteristic of a single Co₂Si nanowire in two- and four-terminal measurements to determine the nanowire resistance and resistivity. The inset shows an SEM image of the device, the scale bar is 3 μm.

Figure 3. Room temperature electrical characteristics of the graphene transistors with a self-aligned nanowire gate

a, An SEM images of a graphene transistor with a self-aligned nanowire gate, the width of devices of about 2.64 μm. The inset shows an optical microscope image the overall device layout. b, The cross-sectional SEM image of a typical device shows the self-aligned Pt thin film source and drain electrodes are well separated by the nanowire gate and precisely positioned next to the nanowire gate. The graphene below the nanowire gate is not clearly visible. c, and d, I_ds-V_TG transfer characteristics at V_ds = −1 V before and after the deposition of the self-aligned Pt source-drain electrodes. e, The I_ds-V_ds output characteristics at various gate voltages (V_TG =0.0, 0.4, 0.8, 1.2, 1.6, and 2.0 V) for the dIds self-aligned device. f, Transconductance $g_m=\left|\frac{{dI}_{ds}}{{dV}_g}\right|$ at V_ds = −1 V as a function of top-gate voltage V_TG before (black) and after (red) the deposition of the self-aligned Pt source-drain electrodes, highlighting the self-alignment process increases the peak transconductance by a factor of > 60. g, Two dimensional plot of the device conductance for varying V_BG and V_TG bias for self aligned device. The unit in the color scale is mS. h, The top-gate Dirac point V_{TG_Dirac} at different V_BG, with which we can derive C_TG/C_BG≈38.

Figure 4. Measured small-signal current gain |h21| as a function of frequency f at V_ds = −1 V

a, For a device with gate length = 144 nm at V_TG = 1 V; b, For a device with gate length = 182 nm at V_TG = 0.3 V; and c, For a device with gate length = 210 nm at V_TG = 1.1 V; These different V_TG values used are the peak transconductance points for each device. The insets show the f_T extraction by Gummel’s method.