An implantable VLSI architecture for real time spike sorting in cortically controlled Brain Machine Interfaces

Abstract

Brain Machine Interface (BMI) systems demand real-time spike sorting to instantaneously decode the spike trains of simultaneously recorded cortical neurons. Real-time spike sorting, however, requires extensive computational power that is not feasible to implement in implantable BMI architectures, thereby requiring transmission of high-bandwidth raw neural data to an external computer. In this work, we describe a miniaturized, low power, programmable hardware module capable of performing this task within the resource constraints of an implantable chip. The module computes a sparse representation of the spike waveforms followed by "smart" thresholding. This cascade restricts the sparse representation to a subset of projections that preserve the discriminative features of neuron-specific spike waveforms. In addition, it further reduces telemetry bandwidth making it feasible to wirelessly transmit only the important biological information to the outside world, thereby improving the efficiency, practicality and viability of BMI systems in clinical applications.