Graphene-Dielectric Integration for Graphene Transistors

Abstract

Graphene is emerging as an interesting electronic material for future electronics due to its exceptionally high carrier mobility and single-atomic thickness. Graphene-dielectric integration is of critical importance for the development of graphene transistors and a new generation of graphene based electronics. Deposition of dielectric materials onto graphene is of significant challenge due to the intrinsic material incompatibility between pristine graphene and dielectric oxide materials. Here we review various strategies being researched for graphene-dielectric integration. Physical vapor deposition (PVD) can be used to directly deposit dielectric materials on graphene, but often introduces significant defects into the monolayer of carbon lattice; Atomic layer deposition (ALD) process has also been explored to to deposit high-κ dielectrics on graphene, which however requires functionalization of graphene surface with reactive groups, inevitably leading to a significant degradation in carrier mobilities; Using naturally oxidized thin aluminum or polymer as buffer layer for dielectric deposition can mitigate the damages to graphene lattice and improve the carrier mobility of the resulted top-gated transistors; Lastly, a physical assembly approach has recently been explored to integrate dielectric nanostructures with graphene without introducing any appreciable defects, and enabled top-gated graphene transistors with the highest carrier mobility reported to date. We will conclude with a brief summary and perspective on future opportunities.

Fig. 1

Graphene as a potential electronic material. (a) Schematic illustration of graphene as an atomic-scale honeycomb lattice of carbon atoms. (b) TEM image of graphene, adapted from [2]. (c) Image of radio frequency devices fabricated on a 2-inch graphene wafer and schematic cross-sectional view of a top-gated graphene FET. (d) Measured small-signal current gain |h₂₁| as a function of frequency f for a 240-nm-gate and a 550-nm-gate graphene FET at V_D = 2.5 V. Cutoff frequencies, f_T, were 53 and 100 GHz for the 550-nm and 240-nm devices, respectively. Adapted from [25].

Fig. 2

Graphene nanostructures for the opening of a conduction gap in graphene.. (a) Schematic view of a graphene nanoribbon and transfer characteristics of a grapnene nanoribbon transistor with on/off ratio >100. (c) Schematic view of a graphene nanomesh and transfer characteristics of a grapnene nanoribbon transistor with on/off ratio >100. Adapted from [34] and [35].

Fig. 3

Raman spectra of the graphene show a clear defect band emerging at 1350 cm⁻¹ after PVD dielectric deposition using various approaches, suggesting significant defects are introduced into graphene lattice during the dielectric deposition process. Adapted from [62].

Fig. 4

(a) SEM image of a graphene transistor with PVD top-gate dielectrics. (b) Back-gate transfer characteristics of Graphene-FET with and without a top gate. Adapted from [58].

Fig. 5

ALD of Al₂O₃ on pristine graphene. (a) AFM image of graphene on SiO₂ before ALD. The height of the triangular shaped graphene is ~1.7 nm as shown in the height profile along the dashed line cut. Scale bar is 200 nm. (b) AFM image of the same area as (a) after ~2 nm Al₂O₃ ALD deposition. The height of the triangular shaped graphene becomes ~−0.3 nm as shown in the height profile along the dashed line cut. Scale bar is 200 nm. (c) and (d) Schematics of graphene on SiO₂ before and after ALD. The Al₂O₃ grows preferentially on graphene edge and defect sites. Adapted from [73].

Fig. 6

(a) (False color) scanning electron microscopy image of the graphene channel and contacts. The inset shows the optical image of the as-deposited graphene flake (circled area) prior to the formation of electrodes. (b) Schematic cross section of the graphene transistor. Note that the device consists of two parallel channels controlled by a single gate in order to increase the drive current and device transconductance. (c) Measured conductance as a function of back-gate voltage, V_BG, of the graphene transistor before depositing the top-gate dielectric. The inset shows the same device after the deposition of Al₂O₃ by ALD. The two arrows represent the sweeping direction of the gate voltage. Adapted from [27].

Fig. 7

ALD of Al₂O₃ on PTCA-coated graphene. (a) Schematic illustration of perylene tetracarboxylic acid (PTCA)-coated graphene. PTCA selectively adheres to graphene on SiO2 surfaces, providing binding sites for TMA deposition. Inset is a top view of PTCA structure. (b) AFM image of graphene on SiO₂ before ALD. The height of the triangular shaped graphene is ~1.6 nm as shown in the height profile along the dashed line cut. Scale bar is 500 nm. (c) AFM image of the same area as (a) after ~2 nm Al₂O₃ ALD deposition. The height of the triangular shaped graphene becomes ~ 3.0 nm as shown in the height profile along the dashed line cut. Scale bar is 500 nm. (d) and (e) Schematics of graphene on SiO₂ before and after ALD. The Al₂O₃ grows uniformly on noncovalently PTCA-coated graphene. Adapted from [73]

Fig. 8

(a) Schematic of dual-gated graphene FET structure. (b) Optical microscope image of a graphene FET. (c) R_tot vs. V_TG data measured at different V_BG values. The inset shows the position of V_Dirac,TG at different V_BG. Optical microscope image of a graphene FET. Adapted from [77].

Fig. 9

(a) Device schematic of the dual-gate graphene transistor. (b) SEM image of a double-channel graphene transistor. The channel width is 27 μm, and the gate length is 350 nm for each channel. (c) Measured channel conductance as a function of the back-gate voltage of a graphene device before and after the deposition of 12-nm-thick ALD Al₂O₃. Prior to the ALD process, a layer of 2-nm aluminum is deposited and oxidized as the nucleation layer. Adapted from [24].

Fig. 10

Two-point back-gated measurements of graphene flakes. (a) Transfer characteristics and corresponding transconductances (inset) after the different stages of buffered dielectric processing: before processing (gray), after NFC polymer deposition (green), after HfO₂ deposition (blue), and after 50 W O₂ plasma treatments for 30 s (red). The schematic shows the completed device configuration. (b) Transfer characteristics of two devices before (solid lines) and after (dashed lines) alternative coating processes are employed. Two nanometers oxidized Al deposition (red) and NO₂ functionalization (blue) is used instead of polymer coating. Both processes result in significant mobility degradation. V_D = 10 mV for all measurements, and V_BG is swept forward and backward to show current hysteresis. Adapted from [14].

Fig. 11

Schematic illustration of the fabrication process to obtain top-gated graphene transistors using dielectric oxide nanostructures (e.g. nanoribbons) as the etching mask and top-gate dielectric. (a) A dielectric nanostructure is aligned on top of graphene using a dry-transfer process without any additional chemical functionalization to minimize the possibility to introduce defects/impurities into the graphene-dielectric interface, and the source-drain electrodes are fabricated by electron-beam lithography. (b) Oxygen plasma etch is used to remove the unprotected graphene, leaving only the graphene underneath the dielectric nanostructure connected to two large graphene blocks underneath the source and drain electrodes. (c) The top gate electrode is defined through lithography and metallization process. Adapted from [89]..

Fig. 12

Evaluation of the Al₂O₃ nanoribbons as dielectric material. (a) TEM image (inset, SAED pattern) and (b) HRTEM image of an Al₂O₃ nanoribbon show nearly perfect crystalline structure with α-Al₂O₃ structure. (c) AFM image of an Al₂O₃ nanoribbon with thickness ~50 nm. The image area is 5 μm × 5 μm. (d) AFM image of the surface of the Al₂O₃ nanoribbon, highlighting the smooth surface with a root mean square roughness < 0.2 nm. The image area is 250 nm × 250 nm. (e) The schematic device diagram (inset) and SEM image of an Al₂O₃ nanoribbon metal-insulator-metal (MIM) device. (f) Current density-electric field (J-E) curve of an MIM device made from an Al₂O₃ nanoribbon, and the inset shows the corresponding Fowler–Nordheim (F-N) curve. Adapted from [89].

Fig. 13

Characterization of the graphene/Al₂O₃ nanoribbon interface. (a) An optical image of an Al₂O₃ nanoribbon on graphene, the scale bar is 2 μm. (b) Raman spectra of the graphene with (b) and without (a) Al₂O₃ nanoribbon covering. There is no D-band in either spectrum, indicating that Al₂O₃ nanoribbon does not introduce any appreciable defects into graphene lattice. (c) A cross-section TEM image of the top gate stack, the scale bar is 100 nm. The inset shows an SEM image of a typical device, the scale bar indicates 5 μm. The dotted line in the inset shows the cross-section cutting direction. (d) A cross-section HRTEM image of the interface between Al₂O₃ nanoribbon and a tri-layer graphene. The partially incomplete graphene layers in the image are caused by electron beam damage during the TEM imaging process. Adapted from [89].

Fig. 14

Room temperature electrical properties of the top-gated graphene device using Al₂O₃ nanoribbon as the gate dielectric. (a) I_ds-V_ds output characteristics, the channel width and length of the device is 2.1μm and 4.1μm (b) Transfer characteristics at V_ds = 1 V for the device using top and back gate (inset). (c) Transconductance g_m as a function of top-gate voltage V_TG, the inset shows the g_m vs. V_BG. The plots indicate the top-gate g_m is about 15 times higher than the back-gate g_m. Adapted from [89].

Fig. 15

Mobility determination in the top-gated graphene device using Al₂O₃ nanoribbon as the gate dielectric. (a) Two-dimensional plot of the device conductance at varying V_BG and V_TG bias. The unit in the color scale is μS. (b) The top-gate Dirac point V_{TG_Dirac} at different V_BG. (c) Experimental plot (black line) and modelling fitting (red line) of R_tot vs. V_TG-V_{TG_Dirac} relation to derive the contact resistance and carrier mobility. Adapted from [89].

Fig. 16

Table summarizing highest mobility values obtained in top-gated graphene transistors using various dielectric integration approaches.

Fig. 17

ZrO₂ NWs as the gate dielectric in top-gated GNR transistors. (a) An SEM image of ZrO₂ nanowires. (b) A TEM image of a ZrO₂ nanowire, and the inset shows the SAED pattern of a ZrO₂ nanowire. (c) The SEM image of a top-gated GNR transistor with ZrO₂ nanowire as top-gate dielectric. The gate length is about 500 nm and the diameter of the nanowire is 50 nm. Inset shows an AFM image of a ~15 nm wide GNR obtained under ZrO₂ nanowire after oxygen plasma etching. The scale bar indicates 200 nm. (d) I_ds-V_ds output characteristics at variable top gate voltage starting from 0.4 V at bottom to −1.0 V at top in the step of −0.2 V. (e) I_ds-V_TG (red curve) and I_ds-V_BG (black curve) transfer characteristics at V_ds = 1 V. (f) Transconductance g_m as a function of top-gate voltage V_TG and back gate voltage V_BG (inset). Adapted from [88].

Fig. 18

Schematic illustration of the fabrication process to obtain top-gated graphene transistors using Si/HfO₂ coreshell nanowires as the etching mask and top-gate. (a) and (e), an Si/HfO₂ coreshell nanowire is aligned on top of graphene using a dry-transfer process, and the source-drain electrodes are fabricated by electron-beam lithography (b) and (f), Oxygen plasma etch is used to remove the unprotected graphene, leaving only the GNR underneath the nanowire connected to two large graphene blocks underneath the source and drain electrodes. (c) and (g), The top-half of the HfO₂ shell was etched away using argon plasma to expose the silicon core gate for contact to external electrode. (d) and (h), The top gate electrode is defined through lithography and metallization process. Adapted from [87].

Fig. 19

TEM characterization of Si/HfO₂ coreshell nanowires. (a) Schematic illustration of the synthesis of Si/HfO₂ coreshell nanowires. Highly doped p-type silicon nanowire arrays were synthesized using catalytic chemical vapour deposition. Atomic layer deposition was used to grow HfO₂ shell with controlled thickness. (b) TEM and (c) HRTEM images of Si/HfO₂ coreshell nanowires. Adapted from [87].

Fig. 20

Characterization of the graphene/HfO₂ interface. (a) A SEM image of a typical device. (b) A cross-section TEM image of the top gate stack. (c) A cross-section HRTEM image of the interface between nanowires and a multi-layers graphene, which indicate that the graphene layers are intimately integrated with the Si/HfO₂ nanowire without any obvious gap or impurities between them. A TEM image of multi-layer graphene device is shown here because it is very difficult to visualize the mono- or few-layer of graphene nanoribbon under the nanowire due to significant electron-beam damage while conducting TEM studies. Adapted from [87].

Fig. 21

Room temperature electrical properties of the top-gated GNR device by using Si/HfO₂ coreshell as the top-gate. (a) Gate leakage current versus top-gate voltage. The leakage current is negligible (at the nA level) within ± 1 V range. (b) I_ds-V_ds output characteristics at variable top-gate voltage starting from 0.6 V at bottom to -1.0 V at top in the step of -0.2 V. (c) The transfer characteristics I_ds-V_TG at V_ds = 0.10 and 1.0 V. (d) I_ds-V_TG and I_ds-V_BG transfer characteristics at V_ds = 1 V. (e) Transconductance as a function of top-gate voltage V_TG and back gate voltage V_BG (inset). (f) Two-dimensional plot of the device conductance at varying V_BG and V_TG bias, the unit in the color scale is μS. Adapted from [87].

Fig. 22

Independently addressable GNR device array. (a) An SEM image of two independently addressable top-gated GNR FETs. (b) Transfer characteristics of two top-gated GNR FETs at V_ds = 0.1 V. (c) The SEM image of a logic OR gates built from GNR transistors. The inset shows the schematic circuit diagram. (d) The OR gate output characteristics with double top-gates. The operating voltage is V_dd = 1V. The inputs for the two gates, A and B, are 1V for state 1 and 0 for state 0. Adapted from [88].