FPGA-Based Pulse Pileup Correction

Abstract

Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for a positron emission tomography (PET) scanner. The University of Washington is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this next generation scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper we report on an all-digital pulse pileup correction algorithm that is being developed for the FPGA. The pileup mitigation algorithm will allow the scanner to run at higher count rates without incurring large data losses due to the overlapping of scintillation signals. This correction technique utilizes a reference pulse to extract timing and energy information for most pileup events. Using pulses were acquired from a Zecotech Photonics MAPDN with an LFS-3 scintillator, we show that good timing and energy information can be achieved in the presence of pileup.

Fig. 1

Block diagram of the overall pulse pileup correction algorithm. Note that number of stages is dependent on the expected rate of pileup.

Fig. 2

Graph of timing resolution for different amount of pulse used for amplitude normalization for a 65MHz sampled pulse.

Fig. 3

Graph of area error as compared to how much of the pulse is interpolated for a 65MHz sampled pulse.

Fig. 4

Graphs indicating the area summation error based on the voltage of the first sample. (a) For a pulse sampled at 65MHz while sampling 20% of the pulse or the whole pulse. (b) For a pulse sampled at 65MHz and 300MHz summing up 20% of the pulse.

Fig. 5

Graph of timing resolution vs. amount of pulse summed with and without the area corrected for the amplitude of the first sample for a 65MHz sampled pulse.

Fig. 6

Graph of area error with and without area correction as compared to how much of the pulse is interpolated for a 65MHz sampled pulse.

Fig. 7

Matlab plot of a pileup streams with 1000kcps from the pulse stream generator routine.

Fig. 8

Timing resolution for different count rates at different ADC sampling rates.

Fig. 9

Plot of timing resolution for a 300MHz ADC sampling for different count rates. The timing resolution is shown for coincidental pulses where neither of the pulse is in a pileup event, where one of the pulses is piled up and where both of the pulses had to be separated from another pulse due to pileup. The overall timing resolution is the combination of all three.

Fig. 10

Graph of the energy resolution of our pulse pileup correction as count rates increase for different ADC sampling rates

Fig. 11

Energy resolution for a 300MHz ADC broken down to pulses in different places of a pileup event.

Fig. 12

Plot of the percentage of pulses that incorrectly determined to not have peak pileup for pileup events in the first 1–20% of the pulse.

Fig. 13

Timing resolution versus count rate for a 300MHz sampling ADC. The top line is for a test that contains peak pileup, while the lower line shows the timing resolution for a test with peak pileup removed.