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. 2010;10(1):16-35.
doi: 10.3390/s100100016. Epub 2009 Dec 24.

Toward 100 Mega-frames per second: design of an ultimate ultra-high-speed image sensor

Vu Truong Son Dao  1 , Takeharu Goji Etoh, Masatoshi Tanaka, Hoang Dung Nguyen, Vo Le Cuong, Kohsei Takehara, Toshiro Akino, Kenji Nishi, Hitoshi Aoki, Junichi Nakai
Affiliations

Toward 100 Mega-frames per second: design of an ultimate ultra-high-speed image sensor

Vu Truong Son Dao et al. Sensors (Basel). 2010.

Abstract

Our experience in the design of an ultra-high speed image sensor targeting the theoretical maximum frame rate is summarized. The imager is the backside illuminated in situ storage image sensor (BSI ISIS). It is confirmed that the critical factor limiting the highest frame rate is the signal electron transit time from the generation layer at the back side of each pixel to the input gate to the in situ storage area on the front side. The theoretical maximum frame rate is estimated at 100 Mega-frames per second (Mfps) by transient simulation study. The sensor has a spatial resolution of 140,800 pixels with 126 linear storage elements installed in each pixel. The very high sensitivity is ensured by application of backside illumination technology and cooling. The ultra-high frame rate is achieved by the in situ storage image sensor (ISIS) structure on the front side. In this paper, we summarize technologies developed to achieve the theoretical maximum frame rate, including: (1) a special p-well design by triple injections to generate a smooth electric field backside towards the collection gate on the front side, resulting in much shorter electron transit time; (2) design technique to reduce RC delay by employing an extra metal layer exclusively to electrodes responsible for ultra-high speed image capturing; (3) a CCD specific complementary on-chip inductance minimization technique with a couple of stacked differential bus lines.

Keywords: CCD; ISIS; backside illumination; high sensitivity; high speed; image sensor.

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Figures

Figure 1.
Figure 1.
Architecture of the ISIS-100M chip.
Figure 2.
Figure 2.
The ISIS-100M structure (a) Front-side ISIS structure (b) Cross-section structure along A-A′ (c) Cross section structure along B-B’.
Figure 3.
Figure 3.
A concentration profile of the gradated double-epi wafer: measurement result by Spreading Resistance (SR) method.
Figure 4.
Figure 4.
Designs of p-well and collection gate. (a), (b), (c): the first, second and third design masks of the p-well; (d) collection gate; and (e) superimposed p-well design. Arrows indicate transfer direction of photoelectrons.
Figure 5.
Figure 5.
Potential profile in the deep part of a fundamental pixel.
Figure 6.
Figure 6.
Cross section profile and an electron path from the backside of the sensor to the collection gate.
Figure 7.
Figure 7.
Function of on-chip micro-lens array concept (k is light collection rate).
Figure 8.
Figure 8.
Electron transit time with on-chip microlens under 10,000e- illuminating condition.
Figure 9.
Figure 9.
Input and output pair of A1 electrode: (a) With two-metal layer at 1 MHz (b) With three-metal layer at 100 MHz.
Figure 10.
Figure 10.
Bus line arrangement of the ISIS-100M.
Figure 11.
Figure 11.
Impedance of A1/A2 bus lines vs. frequency.
Figure 12.
Figure 12.
Twisted differential transmission line structure by Ito et al. [20]
Figure 13.
Figure 13.
Crossed bundling concept for A1 and A2 bus lines.
See this image and copyright information in PMC

References

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