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. 2012 Feb 29;7(1):162.
doi: 10.1186/1556-276X-7-162.

A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires

Chun-Jung Su  1 , Tuan-Kai Su, Tzu-I Tsai, Horng-Chih Lin, Tiao-Yuan Huang
Affiliations

A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires

Chun-Jung Su et al. Nanoscale Res Lett. .

Abstract

In this paper, a silicon-oxide-nitride-silicon nonvolatile memory constructed on an n+-poly-Si nanowire [NW] structure featuring a junctionless [JL] configuration is presented. The JL structure is fulfilled by employing only one in situ heavily phosphorous-doped poly-Si layer to simultaneously serve as source/drain regions and NW channels, thus greatly simplifying the manufacturing process and alleviating the requirement of precise control of the doping profile. Owing to the higher carrier concentration in the channel, the developed JL NW device exhibits significantly enhanced programming speed and larger memory window than its counterpart with conventional undoped-NW-channel. Moreover, it also displays acceptable erase and data retention properties. Hence, the desirable memory characteristics along with the much simplified fabrication process make the JL NW memory structure a promising candidate for future system-on-panel and three-dimensional ultrahigh density memory applications.

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Figures

Figure 1
Figure 1
Illustration of the key process steps for fabricating the JL NW SONOS device. (a) A dielectric stack consisting of top nitride/TEOS/bottom nitride before patterning. (b) Formation of the nano-cavities at the two sides of the stack. (c) Deposition of an n+-doped poly-Si film. (d) Formation of the S/D regions and NW channels by anisotropic dry etching. (e) Final device structure featuring the gate-all-around configuration with an O/N/O gate dielectric stack. (f) Schematic top-view layout of the device.
Figure 2
Figure 2
SEM and TEM characterization of a fabricated JL poly-Si NW device. (a) Top-view SEM image. (b) Cross-sectional TEM image of the NW channel in (a).
Figure 3
Figure 3
Programming properties of the JL and IM NW SONOS devices. (a) Programming characteristics at gate biases of 9, 11, and 13 V. (b) Evolution of the ID-VG curves for the JL device during programming at 13 V from 1 μs to 1 ms.
Figure 4
Figure 4
ID-VG behaviors of the JL NW device. ID-VG behaviors of the JL NW device for multilevel programming operation with gate biases of 9, 11, and 13 V for 100 ns. Inset shows the definition of Vth range for each state.
Figure 5
Figure 5
Erase properties of the JL and IM NW SONOS cells. Before erasing, the cells were programmed to Vth shift of +3 V and +2.5 V for the JL and IM structures, respectively.
Figure 6
Figure 6
Retention behaviors for the JL and IM NW SONOS devices at room temperature.
See this image and copyright information in PMC

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