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. 2012;12(3):2539-60.
doi: 10.3390/s120302539. Epub 2012 Feb 24.

Dual super-systolic core for real-time reconstructive algorithms of high-resolution radar/SAR imaging systems

Alejandro Castillo Atoche  1 , Javier Vázquez Castillo
Affiliations

Dual super-systolic core for real-time reconstructive algorithms of high-resolution radar/SAR imaging systems

Alejandro Castillo Atoche et al. Sensors (Basel). 2012.

Abstract

A high-speed dual super-systolic core for reconstructive signal processing (SP) operations consists of a double parallel systolic array (SA) machine in which each processing element of the array is also conceptualized as another SA in a bit-level fashion. In this study, we addressed the design of a high-speed dual super-systolic array (SSA) core for the enhancement/reconstruction of remote sensing (RS) imaging of radar/synthetic aperture radar (SAR) sensor systems. The selected reconstructive SP algorithms are efficiently transformed in their parallel representation and then, they are mapped into an efficient high performance embedded computing (HPEC) architecture in reconfigurable Xilinx field programmable gate array (FPGA) platforms. As an implementation test case, the proposed approach was aggregated in a HW/SW co-design scheme in order to solve the nonlinear ill-posed inverse problem of nonparametric estimation of the power spatial spectrum pattern (SSP) from a remotely sensed scene. We show how such dual SSA core, drastically reduces the computational load of complex RS regularization techniques achieving the required real-time operational mode.

Keywords: FPGA; parallel computing; remote sensing; super-systolic.

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Figures

Figure 1.
Figure 1.
MPSoC platform of RS algorithms via the HW/SW co-design paradigm.
Figure 2.
Figure 2.
MPSoC platform of RS algorithms via the HW/SW co-design paradigm.
Figure 3.
Figure 3.
Dual SSA core of the RS-related estimator.
Figure 4.
Figure 4.
MAC operation of each PE.
Figure 5.
Figure 5.
Bit-level SSA of the MAC structure.
Figure 6.
Figure 6.
HW-resource scalability analysis: (a) varying the PEs for Virtex-4, (b) varying the PEs for Virtex-5, (c) varying the bits precision for Virtex-4 and (d) varying the bits precision for Virtex-5.
Figure 7.
Figure 7.
Implementation results for the first observation scenario: (SNR μ = 10 dB): (a) Original tested scene; (b) degraded scene image formed applying the MSF method; (c) image reconstructed applying the CLS algorithm; (d) image reconstructed applying the WCLS algorithm.
Figure 8.
Figure 8.
Implementation results for the second observation scenario: (SNR μ = 10 dB): (a) Original tested scene; (b) degraded scene image formed applying the MSF method; (c) image reconstructed applying the CLS algorithm; (d) image reconstructed applying the WCLS algorithm.
See this image and copyright information in PMC

References

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