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. 2012;12(6):7994-8012.
doi: 10.3390/s120607994. Epub 2012 Jun 8.

Compiler optimizations as a countermeasure against side-channel analysis in MSP430-based devices

Pedro Malagón  1 , Juan-Mariano de Goyeneche, Marina Zapater, José M Moya, Zorana Banković
Affiliations

Compiler optimizations as a countermeasure against side-channel analysis in MSP430-based devices

Pedro Malagón et al. Sensors (Basel). 2012.

Abstract

Ambient Intelligence (AmI) requires devices everywhere, dynamic and massively distributed networks of low-cost nodes that, among other data, manage private information or control restricted operations. MSP430, a 16-bit microcontroller, is used in WSN platforms, as the TelosB. Physical access to devices cannot be restricted, so attackers consider them a target of their malicious attacks in order to obtain access to the network. Side-channel analysis (SCA) easily exploits leakages from the execution of encryption algorithms that are dependent on critical data to guess the key value. In this paper we present an evaluation framework that facilitates the analysis of the effects of compiler and backend optimizations on the resistance against statistical SCA. We propose an optimization-based software countermeasure that can be used in current low-cost devices to radically increase resistance against statistical SCA, analyzed with the new framework.

Keywords: MSP430; compiler optimization; embedded system security; hiding countermeasure; side-channel attacks.

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Figures

Figure 1.
Figure 1.
Statistical SCA process.
Figure 2.
Figure 2.
Keeloq power trace (first 12 rounds).
Figure 3.
Figure 3.
CPA using Keeloq power trace.
Figure 4.
Figure 4.
LLVM compilation flow.
Figure 5.
Figure 5.
Number of samples with a similar percentual deviation from common code.
Figure 6.
Figure 6.
Maximum correlation for different key guesses vs. number of power traces with a partial loop unrolling of 2 iterations with MSPSim.
Figure 7.
Figure 7.
Maximum correlation for different key guesses vs. number of power traces with a partial loop unrolling of 2 iterations with MSPSim with 5 cycle window integration.
Figure 8.
Figure 8.
Maximum correlation for different key guesses vs. number of power traces with a partial loop unrolling of 2 iterations.
Figure 9.
Figure 9.
Maximum correlation for different key guesses vs. number of power traces when switching randomly between 3 implementations (2, 3 iterations and no unrolling).
Figure 10.
Figure 10.
Histogram of manipulation of intermediate value.
Figure 11.
Figure 11.
Maximum correlation for different key guesses vs. number of power traces when switching randomly between 3 implementations (2, 3 iterations and no unrolling) attacking with window of size 10.
Figure 12.
Figure 12.
Maximum correlation in region of interest for different key guesses vs. number of power traces when switching randomly between 3 implementations (2, 3 iterations and no unrolling) attacking with window of size 10.
Figure 13.
Figure 13.
Correlation trace for correct key guess using windowed CPA.
See this image and copyright information in PMC

References

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