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. 2013 Mar 4;13(3):3014-27.
doi: 10.3390/s130303014.

SAD-based stereo vision machine on a System-on-Programmable-Chip (SoPC)

Xiang Zhang  1 , Zhangwei Chen
Affiliations

SAD-based stereo vision machine on a System-on-Programmable-Chip (SoPC)

Xiang Zhang et al. Sensors (Basel). .

Abstract

This paper, proposes a novel solution for a stereo vision machine based on the System-on-Programmable-Chip (SoPC) architecture. The SOPC technology provides great convenience for accessing many hardware devices such as DDRII, SSRAM, Flash, etc., by IP reuse. The system hardware is implemented in a single FPGA chip involving a 32-bit Nios II microprocessor, which is a configurable soft IP core in charge of managing the image buffer and users' configuration data. The Sum of Absolute Differences (SAD) algorithm is used for dense disparity map computation. The circuits of the algorithmic module are modeled by the Matlab-based DSP Builder. With a set of configuration interfaces, the machine can process many different sizes of stereo pair images. The maximum image size is up to 512 K pixels. This machine is designed to focus on real time stereo vision applications. The stereo vision machine offers good performance and high efficiency in real time. Considering a hardware FPGA clock of 90 MHz, 23 frames of 640 × 480 disparity maps can be obtained in one second with 5 × 5 matching window and maximum 64 disparity pixels.

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Figures

Figure 1.
Figure 1.
DSP Builder System-Level Design Flow.
Figure 2.
Figure 2.
Proposed SoPC Architecture.
Figure 3.
Figure 3.
The Data Difference between two 5 × 5 windows of the adjacent pixels.
Figure 4.
Figure 4.
Block Diagram of the Disparity Computation Unit.
Figure 5.
Figure 5.
Layout Plan of the Parallel SAD Calculator.
Figure 6.
Figure 6.
Basic Comparison Element of the DS Module.
Figure 7.
Figure 7.
Diagram of the Disparity Segregator.
Figure 8.
Figure 8.
Finite State Machine of the Line Buffer Management.
Figure 9.
Figure 9.
Finite State Machine of the Stereo Matching Process Control.
Figure 10.
Figure 10.
The DSP Development Kit, Cyclone II Edition Boar.
Figure 11.
Figure 11.
Screenshot of the Nios II System.
Figure 12.
Figure 12.
Examples: (a) the original right image; (b) the disparity map computed.
Figure 12.
Figure 12.
Examples: (a) the original right image; (b) the disparity map computed.
See this image and copyright information in PMC

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