Ultrafast synaptic events in a chalcogenide memristor

Abstract

Compact and power-efficient plastic electronic synapses are of fundamental importance to overcoming the bottlenecks of developing a neuromorphic chip. Memristor is a strong contender among the various electronic synapses in existence today. However, the speeds of synaptic events are relatively slow in most attempts at emulating synapses due to the material-related mechanism. Here we revealed the intrinsic memristance of stoichiometric crystalline Ge2Sb2Te5 that originates from the charge trapping and releasing by the defects. The device resistance states, representing synaptic weights, were precisely modulated by 30 ns potentiating/depressing electrical pulses. We demonstrated four spike-timing-dependent plasticity (STDP) forms by applying programmed pre- and postsynaptic spiking pulse pairs in different time windows ranging from 50 ms down to 500 ns, the latter of which is 10(5) times faster than the speed of STDP in human brain. This study provides new opportunities for building ultrafast neuromorphic computing systems and surpassing Von Neumann architecture.

Figure 1. Intrinsic memristance of a crystalline GST-based synapse.

(a) Schematic illustration of a typical biological neuron possessing a cell body (soma), an axon and dendrites. The synapses are the connections between neurons. (b) I-V characteristics measured by DC double sweeping, exhibiting a memristive hysteresis loop. The blue arrows indicate the voltage sweeping directions, and the inset shows the structure of the chalcogenide synapse. (c) Double-logarithmic plot of negative bias (upper) and positive bias (lower) regions exhibiting SCLC behavior. (d) Dependence of capacitance on resistance. The inset shows the frequency dependence of R(ω) (circle symbols) and C(ω) (triangle symbols) at zero bias for HRS (open symbols) and LRS (solid symbols).

Figure 2. Pulse-driven memristive behavior.

The conductance increases or decreases in response to negative or positive pulses, respectively, representing synaptic weight modulation due to potentiating or depressing pulses. The pulse amplitudes vary with identical 30-ns widths and 1-s pulse intervals.

Figure 3. Implementation of STDP with nanosecond-scale time windows in the chalcogenide synapse with the (a), antisymmetric Hebbian learning rule, (b), antisymmetric anti-Hebbian learning rule, (c), symmetric Hebbian learning rule and (d), symmetric anti-Hebbian learning rule.

The red dots indicate the experimental data and the blue lines are the fitted curves. The insets show the pre- and postsynaptic spike schemes and fitting functions.

Figure 4. Tuning of the STDP time window.

(a) A 5 μs time window with a time constant of 1.29 μs. (b) A 500 μs time window with a time constant of 298 μs. (c) A 50-ms time window with a time constant of 35.4 ms. The time constant τ is tuned by modulating the pulse width and interval. The increasing of scaling factor A results from the enhancement of the resistance change variation due to wider pulses that provide more injection charges. (d) Chalcogenide synapse shows its advantages: operating at ultralow voltage and tuning of the time window down to the nanosecond scale, whereas the time window of biological synapse is about 50 ms.