Can we build a truly high performance computer which is flexible and transparent?

Abstract

State-of-the art computers need high performance transistors, which consume ultra-low power resulting in longer battery lifetime. Billions of transistors are integrated neatly using matured silicon fabrication process to maintain the performance per cost advantage. In that context, low-cost mono-crystalline bulk silicon (100) based high performance transistors are considered as the heart of today's computers. One limitation is silicon's rigidity and brittleness. Here we show a generic batch process to convert high performance silicon electronics into flexible and semi-transparent one while retaining its performance, process compatibility, integration density and cost. We demonstrate high-k/metal gate stack based p-type metal oxide semiconductor field effect transistors on 4 inch silicon fabric released from bulk silicon (100) wafers with sub-threshold swing of 80 mV dec(-1) and on/off ratio of near 10(4) within 10% device uniformity with a minimum bending radius of 5 mm and an average transmittance of ~7% in the visible spectrum.

Figure 1. Fabrication process flow of p-type MOSFET on Si (100) fabric.

Detailed description is in the main text.

Figure 2. Scanning electron microscopy images of representative fabrication steps.

(a) Transistor layout after DRIE process showing hole distribution and depth. (Inset-Channel area zoomed-in). (b) ALD-based Al₂O₃ spacer after XeF₂ etching showing isotropic profile. (c) Released ~15 μm silicon fabric after completed XeF₂-based release.

Figure 3. Electrical performance of a representative device on a released fabric (L = 8 μm, W = 5 μm).

(a) I_D–V_G transfer characteristics in logarithmic scale (Inset-Gate leakage density current). (b) I_D–V_G transfer characteristics in linear scale. (c) I_D–V_D curves of same transistor.

Figure 4. Electrical performance comparison of a device before and after release.

(L = 9 μm, W = 5 μm). (a) I_D–V_G transfer characteristics in logarithmic scale. (b) I_D–V_G transfer characteristics in linear scale. (c) Gate leakage density current.

Figure 5

(a) Silicon fabric bended at minimum bending radius of 5 mm. (b) Nominal strain dependence on bending radii.

Figure 6. Bendability dependence of electrical properties of the transistor.

(a) Electrical measurement setup of a silicon fabric at 15 mm bending radius. (b) I_on and I_off behavior under different strain conditions. (c) V_th and S behavior under different strain conditions. (c) Effective mobility versus gate voltage curves for several strain conditions.

Figure 7. Optical characterization.

(a) Silicon fabric with devices (delimited with dashed lines) on top of LED screen showing semi-transparency. (b) Light transmittance versus wavelength in the visible range (Inset-Silicon fabric with devices (delimited with dashed lines) showing diffraction and separation of light into its components as with a diffraction grating).