Single-photon imaging in complementary metal oxide semiconductor processes

Abstract

This paper describes the basics of single-photon counting in complementary metal oxide semiconductors, through single-photon avalanche diodes (SPADs), and the making of miniaturized pixels with photon-counting capability based on SPADs. Some applications, which may take advantage of SPAD image sensors, are outlined, such as fluorescence-based microscopy, three-dimensional time-of-flight imaging and biomedical imaging, to name just a few. The paper focuses on architectures that are best suited to those applications and the trade-offs they generate. In this context, architectures are described that efficiently collect the output of single pixels when designed in large arrays. Off-chip readout circuit requirements are described for a variety of applications in physics, medicine and the life sciences. Owing to the dynamic nature of SPADs, designs featuring a large number of SPADs require careful analysis of the target application for an optimal use of silicon real estate and of limited readout bandwidth. The paper also describes the main trade-offs involved in architecting such chips and the solutions adopted with focus on scalability and miniaturization.

Keywords: avalanche photodiode; complementary metal oxide semiconductor; single-photon avalanche diode.

Figure 1.

FLIM images obtained through TCSPC on a scanned confocal microscope, courtesy of Dr Wolfgang Becker. The colour-coded image shows the lifetime map of a multi-fluorophore-stained sample to evidence certain cellular membrane details.

Figure 2.

Histograms of the response of OGB-1 molecules to repeated excitation in the presence of Ca²⁺ ions at various concentrations [3]. In this case, TCSPC was used to reconstruct the lifetime of the fluorophore OGB-1 as a function of calcium concentration to monitor neuron activity non-destructively. The figure also shows the response of the optical set-up in the absence of fluorophore to characterize its instrument response function (IRF). (Online version in colour.)

Figure 3.

Example of three-dimensional reconstruction obtained using two different optical TOF systems: (a) TCSPC [4,5] and (b) single-photon synchronous detection [8,9]. Both systems detect the returning photons and their time of arrival to derive the overall TOF and thus reconstruct the distance from the camera to the target.

Figure 4.

(a) PET–CT–SPECT system, courtesy of Mediso. (b) Multi-modal PET–MRI image of neck tumour. This medical diagnostic technique uses time-resolved imaging of single photons generated in scintillating crystals when hit by gamma rays that result from nuclear decay.

Figure 5.

I–V characteristics of a diode. Conventional photodiodes operate in linear mode, far below breakdown. APDs and SPADs operate, respectively, slightly below and above breakdown, where the optical gain ranges from a few tens of units to infinity.

Figure 6.

(a) SPAD with passive quenching and recharge circuit and (b) simple quantitative model. The model includes the main internal parasitic components of a SPAD.

Figure 7.

The five phases in the avalanching process: seeding, build-up, spread, quenching and recharge [38]. Voltage at the anode of the pn junction as a function of time (a); current density as a function of the distance from the junction in steps of 1 μm (b). Note the logarithmic time scale. (Online version in colour.)

Figure 8.

Cross section of planar pn junction with electric field simulation (a,b), where the electric field (arb. units) is plotted near the guard ring. In (a), the field exceeds critical values at the edge resulting in PEB, whereas, in (b), it does not [27]. The arb. units scale goes from blue (low field) to red (high field). Light emission test: PEB-prone SPAD (c); PEB-free SPAD (d). The horizontal bar present in both figures is due to the metal connection to the p⁺ layer. The arb. units scale goes from blue (low emission) to red (high emission). (Online version in colour.)

Figure 9.

Premature edge breakdown prevention mechanisms in planar and semi-planar processes. (a) Mechanism was first proposed by Spinelli et al. in [40] and (b) by Cova et al. in [17]. (c) Mechanism was first proposed theoretically by Pauchard et al. in [41] and implemented by Niclass et al. in [25] and by Fishburn in [38], whereas (d) was first proposed by Finkelstein et al. in [26]. Gersbach et al. [27] proposed to encapsulate the STI in multi-layered doped semiconductor material in order to force trap-generated carriers to recombine before reaching the multiplication region. (e) Mechanism was proposed by Richardson et al. in [28] and by Webster in [42]. The grey line represents the limit of the depletion region, within which multiplications can occur.

Figure 10.

(a) SPAD cross section in a conventional CMOS process with the multiplication region highlighted. (b) Passive quench and recharge circuitries as well as pulse shaping. (c) Artist’s rendering of complete SPAD layout.

Figure 11.

Active recharge mechanisms: (a) single-slope and (b) double-slope. In single-slope recharge, a current (I_q) controls the rate of the recharge; the recharge is completed in CV_E/I_q. In double-slope recharge, a small threshold is used to quench the SPAD; it subsequently recharges through I_q, until a second threshold is reached, causing a rapid recharge through switch M_R.

Figure 12.

Photo response in actively recharged SPADs [4], where saturation frequency is f_sat=1/t_dead. Passively recharged SPADs reach saturation at f_sat= 1/e⋅t_dead. A higher saturation is reached by active recharged SPADs as the generated pulses do not merge to reduce, as a result, the overall photon counts.

Figure 13.

Generic pixel and its components. Screamers are turned off by setting an on-pixel memory via the readout/control bus. Analogue and digital counters can be used for uncorrelated photon counting, whereas correlated photon counting requires a TDC or a TAC.

Figure 14.

PDP as a function of excess bias and wavelength in a 130 nm SPAD at room temperature [27]. (Online version in colour.)

Figure 15.

PDE (assuming FF=1) found in the literature for an indicated excess bias voltage [,–54]. (Online version in colour.)

Figure 16.

DCR as a function of excess bias in three chips (a). DCR as a function of temperature and excess bias voltage V_E in an Arrhenius plot (b). The measurements are derived from [52]. (Online version in colour.)

Figure 17.

Dependency of DCR distribution upon exposing a SPAD to gamma radiation generated from a Co-64 source [38]. (a) The DCR distribution for various doses from 0 to 300 kGy. (b) The DCR cumulative distribution in SPADs fabricated in 0.35 μm CMOS technology.

Figure 18.

Timing jitter mechanism. (a) Structure of a slice of the SPAD. (b) Immediate carrier multiplication. (c) Diffusing carrier followed by multiplication. (d) Combination of multiple processes [38].

Figure 19.

Typical timing jitter response in a SPAD: (a) simulated and (b) measured response as a function of the number of detected photons n. The response is the result of the superimposition of Gaussian statistics and an exponential tail. The latter becomes less relevant with the increase of detected photons; hence, jitter is reduced by higher photon fluxes. In the measurements, the number of detected photons is expressed in terms of their expected value E[n], owing to the statistical measurement involved [38]. (Online version in colour.)

Figure 20.

Afterpulsing characterized as a histogram of interarrival times Δt in a typical SPAD after [38]. Afterpulsing relates to the presence of secondary avalanches triggered by the primary ones by trapping and other device non-idealities. (Online version in colour.)

Figure 21.

(a) PDP and (b) dead time uniformity in a 32×32 array of low-pitch passively recharged pixels. PDP variations in the sensor are due to localized breakdown voltage variations, whereas dead time non-uniformity is due to localized variations of parasitics in the recharge circuit of each SPAD. (Online version in colour.)

Figure 22.

Electrical crosstalk mechanism owing to substrate photocarrier exchange. Upon photon absorption, the electron–hole pair is accelerated opposite to each other. The minority carrier is drifting to the depletion region until multiplication can occur; this process, however, may take place in an adjacent pixel thus creating crosstalk. The figure illustrates two photocarriers one of which creates crosstalk. (Online version in colour.)

Figure 23.

Crosstalk characterization around a high DCR pixel before (a) and after suppression of that pixel (b) [12]. Crosstalk was measured as variation of count rate before and after the suppression of a SPAD, generally a high-noise SPAD or screamer. Alternatively, cross-interarrival analysis in pairs of SPADs can also be used to obtain the same result. (Online version in colour.)

Figure 24.

DCR cumulative distribution in a 0.35 μm CMOS process as a function of excess bias [14]. The distribution shows a two-knee behaviour typically observed in most SPAD technologies. By suppressing all those SPADs to the right of the first knee, generally about 15–20% of the SPAD population, a significant improvement of the noise performance of an array can be achieved. Note that the knees in the DCR distribution are generally independent of excess bias voltages. The second knee represents the boundary to screamer pixels that generally represents 0.5–1% of the entire pixel population. (Online version in colour.)

Figure 25.

Timing jitter performance uniformity: FWHM timing jitter over an array of 32 SPADs. A detailed discussion of the avalanching models and the resulting time response can be found in [19] and [38].

Figure 26.

Block diagram and pixel schematic of the 32×32 SPAD array with random access readout.

Figure 27.

A 32×32 SPAD array with random access readout [5,22]. The chip was implemented in 0.8 μm CMOS technology.

Figure 28.

Schematic diagram of the latchless pipelined readout (a); timing diagram and operation of the circuit (b). The detailed description of the pipeline operation, including the symbols used in the schematic and the signals seen in the timing diagram, are described in the corresponding text.

Figure 29.

Demonstrator of latchless pipelined readout implemented in 0.35 μm CMOS technology [66] with SPAD pixels in inset. The chip consists of an array of 16×8 segments of SPADs with an independent readout capability per segment. (Online version in colour.)

Figure 30.

LASP block diagram; it is a fully integrated SPAD array with a bank of TDCs (a); photomicrograph of the chip implemented in 0.35 μm CMOS technology (b). The inset shows the pixel [65]. The chip has a bank of 32 independent TDCs each of which is responsible for time-of-arrival detection in four columns. A high-speed readout circuit transfers all computed time of arrivals to the outside of the chip at 3.2 Gb s⁻¹. (Online version in colour.)

Figure 31.

Block diagram of SwissSPAD (a); schematic diagram of the pixel with embedded one-bit counter and readout circuit (b). The counter is implemented as a static memory. The content of the counter is read out using a simple pulldown transistor and it may be set and reset using appropriate controls [68]. A detailed description of the pixel operation and of the symbols used in the schematics are given in the text.

Figure 32.

Photomicrograph of SwissSPAD, a 512×128 parallel-counting pixel array implemented in 0.35 μm CMOS technology (a); the inset shows a zoom of 4×4 pixels [68]. Printed circuit board bonded device (b). (Online version in colour.)

Figure 33.

Photomicrograph of MEGAFRAME, a 160×128 pixel array, capable of performing one million TOA evaluations per pixel per second at 52 ps time resolution. In the insets, a pixel and 4×4 microlens array are visible. (Online version in colour.)

Figure 34.

The MEGAFRAME chip mounted on a printed circuit board. The microlens array is visible in the centre of the picture. A full characterization of an identical microlens array is reported in [75]. (Online version in colour.)

Figure 35.

SPAD image sensor development landscape based on articles published in the period 2003–2013. The pixel resolution relates to the size of the SPAD array; each technology node is represented by its feature size.