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. 2014 Feb 6:2014:164059.
doi: 10.1155/2014/164059. eCollection 2014.

Facilitating preemptive hardware system design using partial reconfiguration techniques

Affiliations

Facilitating preemptive hardware system design using partial reconfiguration techniques

Julio Dondo Gazzano et al. ScientificWorldJournal. .

Abstract

In FPGA-based control system design, partial reconfiguration is especially well suited to implement preemptive systems. In real-time systems, the deadline for critical task can compel the preemption of noncritical one. Besides, an asynchronous event can demand immediate attention and, then, force launching a reconfiguration process for high-priority task implementation. If the asynchronous event is previously scheduled, an explicit activation of the reconfiguration process is performed. If the event cannot be previously programmed, such as in dynamically scheduled systems, an implicit activation to the reconfiguration process is demanded. This paper provides a hardware-based approach to explicit and implicit activation of the partial reconfiguration process in dynamically reconfigurable SoCs and includes all the necessary tasks to cope with this issue. Furthermore, the reconfiguration service introduced in this work allows remote invocation of the reconfiguration process and then the remote integration of off-chip components. A model that offers component location transparency is also presented to enhance and facilitate system integration.

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Figures

Figure 1
Figure 1
Point to point object communication.
Figure 2
Figure 2
Hardware object adaptation for Remote Method Invocation.
Figure 3
Figure 3
State management of preemptive components.
Figure 4
Figure 4
Dynamic reconfiguration manager.
Figure 5
Figure 5
Dynamic reconfigurable areas layout.
Figure 6
Figure 6
Implicit reconfiguration process.
Figure 7
Figure 7
Remote Network Interface.
Figure 8
Figure 8
Schedule produced by Deadline Monotonic in fully preemptive mode.
Figure 9
Figure 9
Schedule produced by dynamic reconfiguration in fully preemptive mode.
Figure 10
Figure 10
Block diagram of HW-FAST implementation.

References

    1. Dondo JD, Barba J, Rincón F, Moya F, López JC. Dynamic objects: supporting fast and easy run-time reconfiguration in FPGAs. Journal of Systems Architecture. 2013;59(1):1–15.
    1. Ganesan S, Vemuri R. An integrated temporal partioning and partial reconfiguration technique for design latency improvement. Proceedings of the Conference on Design, Automation and Test in Europe (DATE '00); 2000; New York, NY, USA. ACM; pp. 320–325.
    1. Redaelli F, Santambrogio MD, Sciuto D. Task scheduling with configuration prefetching and anti-fragmentation techniques on dynamically reconfigurable systems. Proceedings of the Conference on Design, Automation and Test in Europe (DATE '08); March 2008; New York, NY, USA. ACM; pp. 519–522.
    1. El-Araby E, Gonzalez I, El-Ghazawi T. Exploiting partial runtime reconfiguration for high-performance reconfigurable computing. ACM Transactions on Reconfigurable Technology and Systems. 2009;1(4):21:1–21:23.
    1. Noguera J, Badia RM. Power-performance trade-offs for reconfigurable computing. Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '04); September 2004; New York, NY, USA. ACM; pp. 116–121.

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