Priming and testing silicon patch-clamp neurochips

Abstract

We report on the systematic and automated priming and testing of silicon planar patch-clamp chips after their assembly in Plexiglas packages and sterilization in an air plasma reactor. We find that almost 90% of the chips are successfully primed by our automated setup, and have a shunt capacitance of between 10 pF and 30 pF. Blocked chips are mostly due to glue invasion in the well, and variability in the manual assembly process is responsible for the distribution in shunt capacitance value. Priming and testing time with our automated setup is less than 5 min per chip, which is compatible with the production of large series for use in electrophysiology experiments.