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. 2014 Sep;36(9):1191-6.
doi: 10.1016/j.medengphy.2014.05.002. Epub 2014 Jul 4.

Characterization of a CMOS sensing core for ultra-miniature wireless implantable temperature sensors with application to cryomedicine

Ahmad Khairi  1 , Chandrajit Thaokar  2 , Gary Fedder  1 , Jeyanandh Paramesh  1 , Yoed Rabin  3
Affiliations

Characterization of a CMOS sensing core for ultra-miniature wireless implantable temperature sensors with application to cryomedicine

Ahmad Khairi et al. Med Eng Phys. 2014 Sep.

Abstract

In effort to improve thermal control in minimally invasive cryosurgery, the concept of a miniature, wireless, implantable sensing unit has been developed recently. The sensing unit integrates a wireless power delivery mechanism, wireless communication means, and a sensing core-the subject matter of the current study. The current study presents a CMOS ultra-miniature PTAT temperature sensing core and focuses on design principles, fabrication of a proof-of-concept, and characterization in a cryogenic environment. For this purpose, a 100 μm × 400 μm sensing core prototype has been fabricated using a 130 nm CMOS process. The senor has shown to operate between -180°C and room temperature, to consume power of less than 1 μW, and to have an uncertainty range of 1.4°C and non-linearity of 1.1%. Results of this study suggest that the sensing core is ready to be integrated in the sensing unit, where system integration is the subject matter of a parallel effort.

Keywords: All-CMOS; Cryomedicine; Cryosurgery; Implant; Miniature; Temperature sensor; Ultra low-power.

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Figures

Figure 1
Figure 1
Schematic illustration of the proposed proportional-to-absolute-temperature (PTAT) sensing core
Figure 2
Figure 2
Schematic illustration of the circuit model of the BJT’s in the PTAT including non-ideal parasitic resistances RB1, RB2, RE1 and RE2.
Figure 3
Figure 3
Photograph of the fabricated sensor chip (a) and the packaged chip mounted on PCB (b)
Figure 4
Figure 4
Experimental setup: (a) a schematic illustration of the system, and (b) a photograph of the experimental stage
Figure 5
Figure 5
Results obtained from three representative chips in a self-biased mode (#1 and #2) and an externally biased mode (#2): (a) temperature data as a function of voltage output, and (b) average nonlinear offset, calculated as the temperature difference between the experimental data shown in Fig. (a) and a linear curve connecting the boundary temperature values for each dataset.
See this image and copyright information in PMC

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