A CMOS Neural Interface for a Multichannel Vestibular Prosthesis

Abstract

We present a high-voltage CMOS neural-interface chip for a multichannel vestibular prosthesis (MVP) that measures head motion and modulates vestibular nerve activity to restore vision- and posture-stabilizing reflexes. This application specific integrated circuit neural interface (ASIC-NI) chip was designed to work with a commercially available microcontroller, which controls the ASIC-NI via a fast parallel interface to deliver biphasic stimulation pulses with 9-bit programmable current amplitude via 16 stimulation channels. The chip was fabricated in the ONSemi C5 0.5 micron, high-voltage CMOS process and can accommodate compliance voltages up to 12 V, stimulating vestibular nerve branches using biphasic current pulses up to 1.45±0.06 mA with durations as short as 10 μs/phase. The ASIC-NI includes a dedicated digital-to-analog converter for each channel, enabling it to perform complex multipolar stimulation. The ASIC-NI replaces discrete components that cover nearly half of the 2nd generation MVP (MVP2) printed circuit board, reducing the MVP system size by 48% and power consumption by 17%. Physiological tests of the ASIC-based MVP system (MVP2A) in a rhesus monkey produced reflexive eye movement responses to prosthetic stimulation similar to those observed when using the MVP2. Sinusoidal modulation of stimulus pulse rate from 68-130 pulses per second at frequencies from 0.1 to 5 Hz elicited appropriately-directed slow phase eye velocities ranging in amplitude from 1.9-16.7 °/s for the MVP2 and 2.0-14.2 °/s for the MVP2A. The eye velocities evoked by MVP2 and MVP2A showed no significant difference ( t-test, p=0.34), suggesting that the MVP2A achieves performance at least as good as the larger MVP2.

Fig. 1

Architecture for the Multichannel Vestibular Prosthesis (MVP) system. A mixed-signal application-specific integrated circuit neural interface (ASIC-NI) provides an interface to the afferent fibers located in each semi-circular canal (SCC) of the vestibular labyrinth. The chip incorporates 16 stimulation channels, each with its own 9-bit digital-to-analog converter (DAC) current source or sink. E1, E3, and E5 provide stimulation to the three SCCs, while E2 and E4 are the body and common crus reference electrodes respectively. 11 electrodes remain for expanding stimulation to the cochlea, utricle and saccule, and/or the opposite ear semicircular canals.

Fig. 2

(a) The first generation Multichannel Vestibular Prosthesis, MVP1, occupied 31 mm ×1 mm × 11 mm and consumed 100 mW [5]. (b) Top and bottom views of the 2nd generation MVP2, which decreased in area, thickness and power consumption to 29 mm × 29 mm × 5 mm and 70 mW [16]. The highlighted area on the MVP2 (~866 mm²) indicates discrete analog elements replaced by the (c) 64 mm² QFN56A package for our Application Specific Integrated Circuit neural interface (ASIC-NI) and a photomicrograph of the fabricated chip in this package. The ASIC-NI allows for 48% size reduction in the MVP system size – which provides a significant first step to meet our system size design goals, shown in (d). The outlines in (d), drawn to scale with the MVP1 and MVP2, show the sizes of the hermetic cans of commercially available cochlear implants [25]–[27].

Fig. 3

A high voltage steering circuit based on an augmented differential pair and cascode transistors with lightly doped drains (thick lines). Transistor sizes are indicated next to each transistor. The compliance voltage, Vcomp, can be 5–12 V. The signal dir, supplied by the microcontroller, controls the direction of stimulus current (amplitude set by each channel’s DAC). An additional signal stby, also provided by the microcontroller, is employed to minimize power consumption by putting the interface circuit into a standby state between pulses.

Fig. 4

Representative DAC output from one channel of one ASIC-NI channel. This was recorded with Vcomp set to 12 V and maximal current output at 1.2 mA. Current output was measured using a Source Measurement Unit with the ASIC-NI output clamped at 2.5 V. Over the full range of DAC operation, the output is highly linear (top), differential non-linearity error (DNL, middle) is ≤ 0.8 LSB , and integral non-linearity (INL, bottom) remains within 5 LSB of ideal. The linearity in the DAC is more than adequate for the intended application of the DAC as a programmable interface for a prosthesis.

Fig. 5

Average current output (thick lines) from three ASIC-NIs, three channels from each ASIC-NI (n = 9) using different voltages applied to the compliance voltage pin of the ASIC-NI (V_comp). Current values were measured at 15 input codes with a 120 Ω sense resistor for measuring current, in series with a 1 µF coupling capacitor connected to a 75 µm Pt-Ir wire electrodes with Teflon-insulation stripped 0.2 mm and placed in normal saline (0.9% NaCl). DAC performance is linear for (V_comp) ≥8 V, reaching maximum current levels of around 1.45 ± 0.06 mA. The current output saturates as current is increased when using a V_comp below 8 V. Standard deviations (thin line) ranged from ±2.2% to ±4.5% of the current magnitude. All values were collected using the same pulse rate and pulse duration.

Fig. 6

Two delayed pseudo-monophasic multipolar pulses for current steering [46] using four of the 16 stimulus output channels from the ASIC-NI, delivering pulses at 1 kHz. Although, the MVP uses a mono-polar configuration with charge-balanced, symmetric, biphasic pulses for stimulation this demonstrates the versatility in using the ASIC-N. First phase: 150 µs with the main stimulating source supplying a 1.2 mA cathodic pulse (bottom trace), while return electrodes steer current at 60%, 30%, and 10% returns of the total source. Interphase gap (IPG): 50 µs; Second phase: 450 µs pulse width, main current source at 400 µs to maintain charge balance and return electrodes. Each channel’s load was a 120Ω sense resistor in series with a 1 µF coupling capacitor connected to a 75 µm Pt-Ir wire electrodes with Teflon-insulation stripped 0.2 mm and placed in normal saline (0.9% NaCl).

Fig. 7

Comparison of MVP2 and the ASIC-based MVP stimulator circuitry (MVP2A). Each panel shows cycle-averaged vestibulo-ocular reflex eye movement responses of a stationary, head-fixed monkey (F060738RhG) during 1 Hz sinusoidal modulation of stimulus pulse frequency between 68 and 130 pulses per second (pps) around a baseline of 94 pps (using stimulation parameters detailed in the text), which approximates neural activity that occurs during a 50°/s-peak 1 Hz rotation in normal monkeys [36]. (a, b) Stimulation targeting the horizontal semicircular canal elicits eye movements dominated by the horizontal component. (c, d) Stimulation targeting the left anterior (LA) canal elicits eye movements aligned with the left anterior and right posterior (LARP) SCCs. (e, f) Stimulation targeting the left posterior (LP) canal elicits eye movements aligned with the right anterior and left posterior (RALP) canals. Traces indicate cycle-averaged mean slow phase velocity after removal of saccades and smoothing with a nonlinear low pass filter. Standard deviations are ≤ ±2.4°/s for each trace at each point in time.

Fig. 8

Excitatory (top) and inhibitory (bottom) half-cycle gains for 3D vestibulo-ocular reflex eye movements of monkey F060738RhG evoked by a 0.1–5 Hz sinusoidal modulation of pulse frequency using the parameters described in Fig. 6. Mean responses ranged from 1.9 to 16.7°/s (gain of 0.04–0.33) with the 2nd generation multichannel vestibular prosthesis, MVP2 (solid) and from 2.0 to 14.2°/s (gain of 0.04–0.28) with the ASIC-based MVP system (MVP2A, dashed). Statistical analysis showed no detectable difference (t-test, p = 0.34) between the VOR gains produced by the MVP2 versus the MVP2A.