Modeling and Experimental Demonstration of a Hopfield Network Analog-to-Digital Converter with Hybrid CMOS/Memristor Circuits

Abstract

The purpose of this work was to demonstrate the feasibility of building recurrent artificial neural networks with hybrid complementary metal oxide semiconductor (CMOS)/memristor circuits. To do so, we modeled a Hopfield network implementing an analog-to-digital converter (ADC) with up to 8 bits of precision. Major shortcomings affecting the ADC's precision, such as the non-ideal behavior of CMOS circuitry and the specific limitations of memristors, were investigated and an effective solution was proposed, capitalizing on the in-field programmability of memristors. The theoretical work was validated experimentally by demonstrating the successful operation of a 4-bit ADC circuit implemented with discrete Pt/TiO2- x /Pt memristors and CMOS integrated circuit components.

Keywords: Hopfield network; analog-to-digital conversion; hybrid circuits; memristor; recurrent neural network; resistive switching.

Figure 1

(A) Conventional Hopfield network implementation of a 4-bit ADC and (B) specific implementation of a neuron as considered in this paper.

Figure 2

(A) Typical I-V curves with current-controlled set and voltage-controlled reset switching for the considered Pt/TiO_2−x/Pt memristors. (B) Modeling of static I-V curves at small disturb-free voltages for several different states. The fitting parameters are β = 1, α₁ = 14.7 V⁻³, ${\alpha }_2=-5.9\times 10^4$ ΩV⁻³,${\alpha }_3=1.5\times 10^8$ Ω²V⁻³ for V > 0, and α₁ = 34.6 V⁻³, ${\alpha }_2=-1.9\times 10^5$ ΩV⁻³, ${\alpha }_3=3.65\times 10^8$ Ω²V⁻³ for V < 0.

Figure 3

Theoretical analysis of the performance sensitivity of a 4-bit Hopfield network ADC with respect to (A) open-loop DC gain, (B) voltage offsets in the operational amplifiers, and (C) the nonlinearity of memristive devices.

Figure 4

Simulation results for (A) the original and (B) the optimized 4-bit Hopfield network ADC with β = 1, $A_{\text{DC}}=2\times 10^5$, and u_o = 3 mV voltage offset, which are representative parameters for the experimental setup. For the optimized network, T_R” = 0.97 T_R1, T_R2” = 0.86 T_R2, T_R3” = 0.95 T_R3, T_R4” = 0.97 T_R4.

Figure 5

Simulation results for the optimized 8-bit Hopfield network ADC with T_R1” = 0.8 T_R1, T_R2” = 0.81 T_R2, T_R3” = 0.89 T_R3, T_R4” = 0.83 T_R4, T_R5” = 0.55 T_R5, T_R6” = 0.74 T_R6, T_R7” = 0.71 T_R7, T_R8” = 0.75 T_R8. All other parameters are equal to those used for Figure 4.

Figure 6

Experimental results for the optimized 4-bit Hopfield ADC: (A) experimental setup, (B) measured outputs for every output channel, and (C) measured transfer characteristics.