Unsupervised Learning by Spike Timing Dependent Plasticity in Phase Change Memory (PCM) Synapses

Abstract

We present a novel one-transistor/one-resistor (1T1R) synapse for neuromorphic networks, based on phase change memory (PCM) technology. The synapse is capable of spike-timing dependent plasticity (STDP), where gradual potentiation relies on set transition, namely crystallization, in the PCM, while depression is achieved via reset or amorphization of a chalcogenide active volume. STDP characteristics are demonstrated by experiments under variable initial conditions and number of pulses. Finally, we support the applicability of the 1T1R synapse for learning and recognition of visual patterns by simulations of fully connected neuromorphic networks with 2 or 3 layers with high recognition efficiency. The proposed scheme provides a feasible low-power solution for on-line unsupervised machine learning in smart reconfigurable sensors.

Keywords: cognitive computing; memristor; neural network; neuromorphic circuits; pattern recognition; phase change memory; spike timing dependent plasticity.

Figure 1

Cross sectional view of a PCM obtained by transmission electron microscopy (TEM) (A), measured quasi-stationary I-V curves for the PCM device in the crystalline and amorphous phase (B), reset characteristic of R as a function of the write voltage for pulse-width 40 ns (C) and set characteristics of R as a function of the set pulse-width t_P and voltage V_set = 1.05 V for variable initial PCM state (D). The PCM device shows fast switching at low voltage, thus supporting PCM technology for low-voltage, low-power synapses in neuromorphic systems.

Figure 2

Schematic illustration of the neuromorphic network with a 1T1R synapse. The PRE drives the MOS transistor gate voltage V_G, thus activating a current spike due to the low negative TE voltage (V_TE = −30 mV) set by the POST. The current spikes are fed into the POST, which eventually delivers a V_TE spike back to the synapse as the internal voltage V_int exceeds a threshold V_th. The V_TE spike includes a set and reset pulse to induce potentiation/depression according to the STDP protocol.

Figure 3

Scheme of the applied pulses from the PRE and POST neurons to the 1T1R synapse. In the case of small positive delay Δt (A), when the PRE spike is applied just before the POST spike, the PCM receives a potentiating pulse with voltage V_set inducing set transition. On the other hand, for small negative delay Δt (B), when the PRE spike is applied just after the POST spike, the PCM receives a depressing pulse with voltage V_reset inducing reset transition. For positive/negative delays larger than 10 ms, there is no overlap between PRE and POST spikes, thus no potentiation/depression can take place.

Figure 4

STDP characteristics, namely measured change of conductance R₀/R as a function of delay Δt, for various PCM states, namely state A (R₀ = 15 kΩ), state B (R₀ = 500 kΩ), and state C (R₀ = 10 MΩ), also reported in Figure 1D. Depression and/or potentiation are shown depending on delay and initial state, providing a confirmation of the STDP capability in our 1T1R synapse.

Figure 5

Result of a random spiking experiment, showing the random delay Δt as a function of the epoch (A), corresponding synapse resistance as a function of the epoch (B), and correlation between Δt and R₀/R (C). The correlation between delay and conductance change is consistent with the STDP characteristics at variable resistance in Figure 4.

Figure 6

Neuromorphic network adopted in our simulations: schematic illustration (A) and corresponding circuit (B). A first neuron layer with N = 28 × 28 neurons is fully connected to a second neuron layer with M neurons through 1T1R PCM-based synapses. The first layer delivers spikes in response to presentation of one or more visual patterns. During training, STDP within the synapses leads to LTP/LTD update of the synapse weights eventually resulting in the specialization of the output neurons in recognizing the submitted patterns.

Figure 7

Simulation results for pattern learning. The input pattern “1” (A) is presented at the input together with noise (B). Synaptic weights are random at t = 0 s (C), then they specialize at progressive times 3.5 s (D) and 7 s (E). The corresponding complete evolution of synapse weights for increasing time is shown in (F), with positions A, B, and C related to (C–E). Red lines represent synapses for pattern, cyan lines are the background synapses, while the black and blue lines are the mean pattern and background synapses, showing progressive learning and specialization.

Figure 8

Energy E_syn and mean power P_syn per synapse as a function of time during the learning process of Figure 7 (A) and corresponding histogram distribution of energy consumption E_{syn, c} due to communication from 4.2 s to 7 s, namely after completing potentiation/depression (B). Consumption due to communication (in red) is directly induced by PRE spikes, while fire energy (in blue) corresponds to set/reset events induced by POST spikes. The energy histogram reveals 3 energy levels: Group I around 80 pJ reflects communication of pattern spikes at potentiated synapses. Group II around 5 pJ represents communication of noise spikes at potentiated pattern synapses, while group III just below 100 fJ corresponds to noise spikes at depressed background synapses.

Figure 9

Simulation results for pattern learning and updating. Pattern “1” and noise (A) were presented for the first 7 s, followed by pattern “2” (B) and noise for the last 7 s. After the first 7 s, in A, pattern “1” was learnt (C). After starting with “2,” synapses showed a mixed specialization at 7.5 s in B (D), where “1” was being forgotten and “2” was being learned. Finally, at 14 s in C (E), “2” was learnt. (F) shows the temporal evolution of synapses, with initial learning of “1,” followed by updating with “2.”

Figure 10

Simulation results for multiple pattern learning. A first layer with 28 × 28 = 784 neurons is fully connected to three second layer neurons, each of them connected with three inhibitory synapses (A). We provided three patterns “1,” “2,” and “3” (B) to the input. The three neurons specialize on different patterns (C). (D) shows the evolution of the synapses connected to one of the post neurons, in particular the mean weight for synapses of pattern “1,” “2,” “3” and background. While the background gradually decreases, the learnt pattern (the highest mean conductivity) changes during time due to interference between patterns.

Figure 11

Scheme for implementing low energy consumption communication. Instead of applying a constant V_TE = −30 mV, sequences of spikes lasting t_spike can allow for efficient communication (A), while reducing energy and power consumption by a factor t_spike/T_spike, where T_spike is the time between adjacent pulses (B).

Figure 12

Multi-layer simulation results. The number n of PRE spikes is composed by n_p pattern and n_n noise inputs. n_p is composed by n_{p, f} (pattern leading to output spike) and n_{p, 0} (missing recognition). n_n is composed by n_{n, f} (false recognition) and n_{n, 0} (absence of spike for input noise) (A). After an input layer with 28 × 28 neurons, a second layer with variable M neurons and a third layer with one output neuron are implemented (B). The recognition rate P_learn = n_{p, f}/n_p increases with respect to the two layers network and it increases for increasing number M of second layer neurons (C), while the error rate P_err = n_{n, f}/n_n decreases (D). P_learn further increases for optimized conditions (lower noise), reaching a 95.5% recognition, while P_err drops to 0.35%.

Figure 13

Probability of recognizing an input pattern P_learn, solid line, and probability of spurious fires P_err, dashed line, as a function of input noise.