FPGA-based RF interference reduction techniques for simultaneous PET-MRI

Abstract

The combination of positron emission tomography (PET) and magnetic resonance imaging (MRI) as a multi-modal imaging technique is considered very promising and powerful with regard to in vivo disease progression examination, therapy response monitoring and drug development. However, PET-MRI system design enabling simultaneous operation with unaffected intrinsic performance of both modalities is challenging. As one of the major issues, both the PET detectors and the MRI radio-frequency (RF) subsystem are exposed to electromagnetic (EM) interference, which may lead to PET and MRI signal-to-noise ratio (SNR) deteriorations. Early digitization of electronic PET signals within the MRI bore helps to preserve PET SNR, but occurs at the expense of increased amount of PET electronics inside the MRI and associated RF field emissions. This raises the likelihood of PET-related MRI interference by coupling into the MRI RF coil unwanted spurious signals considered as RF noise, as it degrades MRI SNR and results in MR image artefacts. RF shielding of PET detectors is a commonly used technique to reduce PET-related RF interferences, but can introduce eddy-current-related MRI disturbances and hinder the highest system integration. In this paper, we present RF interference reduction methods which rely on EM field coupling-decoupling principles of RF receive coils rather than suppressing emitted fields. By modifying clock frequencies and changing clock phase relations of digital circuits, the resulting RF field emission is optimised with regard to a lower field coupling into the MRI RF coil, thereby increasing the RF silence of PET detectors. Our methods are demonstrated by performing FPGA-based clock frequency and phase shifting of digital silicon photo-multipliers (dSiPMs) used in the PET modules of our MR-compatible Hyperion II (D) PET insert. We present simulations and magnetic-field map scans visualising the impact of altered clock phase pattern on the spatial RF field distribution, followed by MRI noise and SNR scans performed with an operating PET module using different clock frequencies and phase patterns. The methods were implemented via firmware design changes without any hardware modifications. This introduces new means of flexibility by enabling adaptive RF interference reduction optimisations in the field, e.g. when using a PET insert with different MRI systems or when different MRI RF coil types are to be operated with the same PET detector.

Figure 1.

Singles detection module fully equipped with six detector stacks and removed carbon fibre shielding.

Figure 2.

(a) One complete detector stack (exploded view). PCB images taken from Weissler et al (2015a). (b) A sensor tile consisting of 16 sensor dies with one of them visualised by a white square. (c) A single sensor die.

Figure 3.

Clocking infrastructure of the PET insert visualised for the reference clock (refCLK) and refCLK-derived clocks at PET system, SDM and stack levels. Arrows with dashed lines indicate clocking-related control signals, arrows with full lines indicate clock signal paths. At SDM level, the number of individual stack refCLK signal lines on the SPU is indicated by the number Six below the signal line close to the fan-out chip. The frequency and phase of the clock signals can be modified in each FPGA via integrated clock synthesizer and phase shifter blocks.

Figure 4.

Measured reflection coefficient (S11, magnitude) as a function of frequency for the birdcage resonator. The resonance spectrum includes resonance modes at which an energy transmission to the RF resonator is highly efficient. The mode that provides a homogeneous RF field distribution and is therefore used for spin excitation is highlighted with a grey-shaded area. In contrast, the modes at lower frequencies do not provide a homogeneous field distribution and are therefore not of interest for MRI applications. Hence, a band-pass filter (also indicated by the grey-shaded area) is applied around the Larmor frequency at 3 T. To avoid noise coupling, the sensor die clock frequency is shifted in such a way that as little energy as possible is emitted in the frequency region of the band-pass filter.

Figure 5.

Phase-shift approach at stack level: each of the 16 squares represents a sensor die, which is modelled as a dipole loop. (a) The actual sensor tile with the PET sensor dies as seen from above. (b) The usage of an in-phase pattern. (c) A checkerboard-phase pattern.

Figure 6.

(a) The RF coil screen with the RF coil taken out and placed next to it (image taken from Wehner et al (2015)). (b) The FEKO simulation model.

Figure 7.

Phase pattern schemes at SDM level for an SDM with six stacks: compared to the default sensor die clocking where no phase shift is applied (a) is a sensor die clock pattern with ${180}^{°}$ clock phase shifts for complete stacks (stack level) to obtain a checkerboard pattern (b).

Figure 8.

Overview of the laboratory bench setup used for RF field map and RF broadband measurements. Not shown in the picture are the cooling unit and the control PC running Hyperion software, which is connected to the SDM on the laboratory bench.

Figure 9.

Closeup view of the SDM positioned on the laboratory bench setup as seen in figure 8: the XYZ table moves the magnetic-field probe along the left and top planes to cover in-plane positions with a 5 mm step. Afterwards, the SDM is turned with the detector stacks in the direction of the laboratory bench to repeat the measurement.

Figure 10.

A single SDM without carbon fibre shielding mounted on a PET gantry to make MRI noise measurements. The RF coil was connected via coil electronics to the MRI RF subsystem.

Figure 11.

Calculated field emissions of a sensor tile given at a distance of 35 cm: (a) the result for applied in-phase pattern clocking with amplitudes with an order of magnitude of  −3; (b) a quadrupole-arranged field emission when checkerboard-pattern clocking is applied. The amplitudes’ order of magnitude in (b) is  −7.

Figure 12.

Simulated surface current distributions of the RF screen and the coil resulting from field emission by dipoles (visualised as red arrows) in front of the RF screen. (a) Field pattern generated by the in-phase pattern leads to distribution over entire the RF screen. (b) Checkerboard-pattern-related field emission yields a localised current distribution.

Figure 13.

Mean singles rates obtained with firmware designs implementing different sensor die frequencies as given in section 3.3.1. The error bars are given as standard deviations.

Figure 14.

EM emission of the SDM measured with a spectrum analyser for different sensor die clock frequencies. (a) The broadband measurement with the sensitive bandwidth of the 3 T MRI highlighted by the grey-shaded area around 127.78 MHz. (b) The laboratory bench results for a frequency range within the 3 T-MRI-sensitive bandwidth excluding the die clock frequency equal to the Larmor frequency for the worst-case scenario.

Figure 15.

Field map measurement results (x component of the emitted H field) for sensor die clocking with in-phase pattern (a) and checkerboard-phase pattern (b) at SDM level and a sensor die clock frequency of 127.78 MHz.

Figure 16.

Field map measurement results (y component of the emitted H field) for sensor die clocking with in-phase pattern (a) and checkerboard-phase pattern (b) at SDM level and a sensor die clock frequency of 127.78 MHz.

Figure 17.

Noise scan results performed for sensor die clock frequencies between 100 and 200 MHz. The SDM was powered off during the noise reference scan.

Figure 18.

(a) MRI noise scan results for an SDM clocked at 127.78 MHz in-phase and with applied checkerboard pattern at SDM level. (b) Ratio of the noise floors shown in (a).

Figure 19.

MRI phantom images with low SNR acquired while (a) the SDM is powered off, (b) the SDM operates with a sensor die clock frequency of 160 and (c) the SDM operates with sensor dies clocked at 140 MHz.

Figure 20.

Signal intensities across a horizontal line profile crossing the MRI phantom: The noise floor varies depending on the sensor die clock frequency generated by the SDM firmware.