Approaching Defect-free Amorphous Silicon Nitride by Plasma-assisted Atomic Beam Deposition for High Performance Gate Dielectric

Abstract

In the past few decades, gate insulators with a high dielectric constant (high-k dielectric) enabling a physically thick but dielectrically thin insulating layer, have been used to replace traditional SiOx insulator and to ensure continuous downscaling of Si-based transistor technology. However, due to the non-silicon derivative natures of the high-k metal oxides, transport properties in these dielectrics are still limited by various structural defects on the hetero-interfaces and inside the dielectrics. Here, we show that another insulating silicon compound, amorphous silicon nitride (a-Si3N4), is a promising candidate of effective electrical insulator for use as a high-k dielectric. We have examined a-Si3N4 deposited using the plasma-assisted atomic beam deposition (PA-ABD) technique in an ultra-high vacuum (UHV) environment and demonstrated the absence of defect-related luminescence; it was also found that the electronic structure across the a-Si3N4/Si heterojunction approaches the intrinsic limit, which exhibits large band gap energy and valence band offset. We demonstrate that charge transport properties in the metal/a-Si3N4/Si (MNS) structures approach defect-free limits with a large breakdown field and a low leakage current. Using PA-ABD, our results suggest a general strategy to markedly improve the performance of gate dielectric using a nearly defect-free insulator.

Figure 1

TEM, PL, and optical E_g characterizations: (a,b) are cross-sectional HRTEM images of PA-ABD a-Si₃N₄ grown on Si (100) and Si (111) substrates with pre-treatment at high temperature (600 °C) and lower temperature (950 °C), respectively. (c) Room temperature PL spectra for the PA-ABD a-Si₃N₄/Si (100) (red), the PA-ABD a-Si₃N₄/Si (111) (blue), the PECVD a-SiN_x/Si (111) and bare Si (100) and Si (111) substrates (black curve). (d) Optical E_g measurement of PA-ABD a-Si₃N₄ with red circles for experimental data, black curve for fitting) by UV-visible absorption spectra. The blue curve is previously reported data for the stoichiometric a-Si₃N₄. The inset is the photo of the PA-ABD a-Si₃N₄ membrane for the transmission measurement.

Figure 2

Band structure analysis: μ-PES spectra of the Si 2p core-level taken on cross-sectional PA-ABD a-Si₃N₄/Si(111) (a) and PECVD a-SiN_x/Si(111) (b) samples for clean interface and bulk regions. SR-PES spectra of the Si 2p core-level taken on PA-ABD a-Si₃N₄ (c) and PECVD a-SiN_x (d) surfaces for obtaining energy differences between the Si 2p core-level and the valence-band maxima (E_CL-E_VBM). Schematic illustration of the XSPEM and SR-PES on the PA-ABD a-Si₃N₄/Si(111) and PECVD a-SiN_x/Si(111) samples are included in the left panel of the Figure. The corresponding decomposition of Si 2p states for a-Si₃N₄ and a-SiN_x are also shown. The leading edges of valence bands for determining E_VBM from a-Si₃N₄ and a-SiN_x can be observed in the insets of (c,d), respectively. The black dots are the experimentally spectral data points and color lines are the curve-fitting results. (e) The schematic energy band diagram of a-SiN_x/Si(111), a-Si₃N₄/Si(111), and a-Si₃N₄/Si(100) based on the measured values of ΔE_CL, E_CL-E_VBM, in (a–d), and the crystalline orientated EA value of Si bulk.

Figure 3

Leakage current and surface morphology characterizations: (a) Leakage gate current densities and breakdown fields for the 10-nm thick PA-ABD a-Si₃N₄ grown on Si (111) (black curve) and Si (100) (blue curve). The top inset is the schematic energy band diagram of the MNS capacitor with a p-type substrate for a negative gate bias. The AFM images taken on the corresponding a-Si₃N₄ layers with (b) and without (c) surface steps grown on Si (111) and Si (100), respectively. The average height profiles are shown below the images and the scale bars indicate for 100 nm of length.

Figure 4

Gate current densities modeling and EOT analysis: (a) Model the gate current densities for 2.1 nm of PA-ABD a-Si₃N₄ on the p-type Si (100) substrate with dots for experimental data and with red curve for the model of direct tunneling. The top inset is the energy band diagram of the MNS capacitor with a p-type substrate for a negative gate bias, and the bottom inset is cross sectional HR TEM image. (b) Plot of leakage current density at 1V of gate voltage versus EOT for SiO₂, HfO₂, and PA-ABD a-Si₃N₄ for comparison, and PA-ABD a-Si₃N₄ shows a significant leakage current reduction. The criteria of low power limit and gate limit of leakage current densities are taken from previous reports.