Polarity control in WSe2 double-gate transistors

Abstract

As scaling of conventional silicon-based electronics is reaching its ultimate limit, considerable effort has been devoted to find new materials and new device concepts that could ultimately outperform standard silicon transistors. In this perspective two-dimensional transition metal dichalcogenides, such as MoS2 and WSe2, have recently attracted considerable interest thanks to their electrical properties. Here, we report the first experimental demonstration of a doping-free, polarity-controllable device fabricated on few-layer WSe2. We show how modulation of the Schottky barriers at drain and source by a separate gate, named program gate, can enable the selection of the carriers injected in the channel, and achieved controllable polarity behaviour with ON/OFF current ratios >10(6) for both electrons and holes conduction. Polarity-controlled WSe2 transistors enable the design of compact logic gates, leading to higher computational densities in 2D-flatronics.

Figure 1. WSe₂ flake properties and device fabrication.

(a) AFM topography image of the exfoliated flake after cleaning of tape residues with hot (50 °C) acetone bath. The red line indicated the cutline used to extract the flake thickness. (b) Height profile for the cutline showed in a. The extracted flake thickness is 7.5 nm, which corresponds to ~10 monolayers. (c) Optical image of the realized device. The channel length, including all gated regions, is 1.5 μm long of which 1 μm is gated by the bulk-Si (acting as the CG) and two 0.25 μm regions, near the contacts, are controlled by the buried program gate (horizontal parallel metal lines marked as PG). The red dotted line indicated the cutline used to represent the device schematic. (d) 3D-schematic cross-section of the device along the red cutline in (c).

Figure 2. Characterization of ambipolar behavior.

(a) Transfer characteristics of a back-gates device fabricated with a 6 nm thick WSe₂ flake exfoliated on 20 nm SiO₂ substrate before and after annealing. The hole current is improved by 1 order of magnitude and the electron current remains unvaried. In this case, the positive and negative V_g sweeps were taken separately, thus the non-continuity of the curves at V_g = 0 V. Both curves were taken with V_DS = 1 V. (b) Transfer characteristic of the double-gate device presented in Fig. 1 measured with floating program gates. The device shows a good ambipolar behaviour, with ON currents of 4 μA for electrons and of 0.25 μA for holes. The OFF current is well below the pA range (100 fA). The three coloured dots mark the 3 operating regions in this configuration: OFF state (red), ON state n-type (yellow) and ON state p-type (green). The inset shows the electrical connections used during the measurement.

Figure 3. Device characteristics.

(a,b) Transfer characteristics of the device obtained for different negative (a) and positive (b) voltage values applied to the program gate as a function of the control gate bias. The inset in (a) shows the connection used for the measurements. The dashed squares represent the 4 region of operation (ON p-type, OFF p-type, OFF n-type, ON n-type) of the transistor for which the corresponding band-diagram is shown in (c–f). The transparent colored circles report the current values extracted from Fig. 2(b) and show how the current levels are not altered by the polarity-control mechanism. (c–f) Band-diagrams of the 4 region of operation.

Figure 4. Polarity change “on-the-fly” and XOR behaviour.

(a) Transfer characteristics obtained for fixed values of the control gate bias and sweeping the program gate voltage. We can see how for V_CG = 0 the device shows its OFF-state ambipolar behaviour by conducting both electrons and holes, according to the value of V_PG. The inset shows the measurement configuration. (b) 3D view of the device switching properties, highlighting the XOR operation based on the values of the program and control gates. The inset shows the truth table of the pseudo-logic function implemented.