Magnetic Tunnel Junction Based Long-Term Short-Term Stochastic Synapse for a Spiking Neural Network with On-Chip STDP Learning

Abstract

Spiking Neural Networks (SNNs) have emerged as a powerful neuromorphic computing paradigm to carry out classification and recognition tasks. Nevertheless, the general purpose computing platforms and the custom hardware architectures implemented using standard CMOS technology, have been unable to rival the power efficiency of the human brain. Hence, there is a need for novel nanoelectronic devices that can efficiently model the neurons and synapses constituting an SNN. In this work, we propose a heterostructure composed of a Magnetic Tunnel Junction (MTJ) and a heavy metal as a stochastic binary synapse. Synaptic plasticity is achieved by the stochastic switching of the MTJ conductance states, based on the temporal correlation between the spiking activities of the interconnecting neurons. Additionally, we present a significance driven long-term short-term stochastic synapse comprising two unique binary synaptic elements, in order to improve the synaptic learning efficiency. We demonstrate the efficacy of the proposed synaptic configurations and the stochastic learning algorithm on an SNN trained to classify handwritten digits from the MNIST dataset, using a device to system-level simulation framework. The power efficiency of the proposed neuromorphic system stems from the ultra-low programming energy of the spintronic synapses.

Figure 1. A typical SNN consisting of an array of pre-neurons and post-neurons interconnected by synapses that are modeled as multilevel conductance.

The pre-synaptic voltage spike (V_pre) is modulated by the synaptic conductance (w) to generate a resultant post-synaptic current (I_post). The post-neuron integrates the current leading to an increase in its membrane potential (V_mem), and spikes if the potential exceeds a certain threshold voltage (θ).

Figure 2

(a) The dynamics of the membrane potential of a post-neuron, which increases upon the arrival of an input pre-synaptic spike and decays subsequently. The post-neuron fires a spike if its membrane potential exceeds a definite threshold (θ). The potential is thereafter reset (V_rst) and the neuron is restrained from spiking for a duration of time termed the refractory period. Synaptic potentiation depends on the period of time elapsed between a post-neuron spike and the most recent pre-synaptic spike (t_post–t_pre). (b) Hierarchical SNN topology for pattern recognition consisting of input, excitatory, and inhibitory layers. The input layer is fully connected to the excitatory neurons, which are connected to the corresponding inhibitory neurons in a one-to-one manner. Each of these neurons inhibits all the excitatory neurons except the one from which it received a forward connection.

Figure 3

(a) Cross-sectional view of an MTJ-HM binary synapse. The read (spike-transmission) current flowing between the terminals V_READ and GND is modulated by the MTJ conductance, while the write (programming) current flowing between terminals V_PROG and GND stochastically switches the magnetization of the free layer. (b) A significance driven LT-ST stochastic synapse comprising two MTJ-HM devices. The LT synapse is driven by a relatively higher read voltage (V_{READ_LT} > V_{READ_ST}; β > 0.5), thereby leading to a larger post-synaptic current.

Figure 4

(a) The switching probability of the free layer magnetization of the MTJ due to a programming current flowing through the HM underlayer. (b) Change in the MTJ resistance upon the application of a 40 μA current pulse for a duration of 1 ns.

Figure 5. Stochastic STDP dynamics of a one-bit synapse, wherein the probability of potentiation and depression is exponentially related to the difference in the spike times of a post-neuron (t_post) and pre-neuron (t_pre).

Figure 6. STDP dynamics of an LT-ST stochastic synapse.

(a) The LT synapse has a sharper rate of potentiation that enables it to learn strongly correlated input patterns while the ST synapse potentiates with a greater probability for larger spike time differences to acquire moderately correlated features. (b) The LT synapse has a steeper rate of depression to reliably retain the acquired information while the ST synapse has a larger depression probability over the negative STDP timing window.

Figure 7

(a) Implementation of the stochastic STDP algorithm. The control signal V_{PRE_POT} resets the node voltage V_{PROG_POT} following an input pre-neuron spike. Once M_{PRE_POT} turns off, V_{PROG_POT} increases linearly at a rate determined by C_POT and the bias voltage V_{T_POT}. The access transistors M_A1–M_A2 are enabled by the control signal WRITE_WL, which is asserted high at an appropriate instant following a spike fired by the connected post-neuron. Finally, V_{PROG_POT} that is proportional to the elapsed time period between a pair of pre-and post-neuron spikes (t_post–t_pre) is sampled by M_POT to generate the required write current I_POT. A similar discussion is valid for the depression circuit, wherein the programming current is passed in the opposite direction. (b) Bitcell configuration of an MTJ-HM binary synapse. The bitline POT_BL drives the potentiation circuit path, which is conditionally enabled by the write wordline (WRITE_WL). The reference bitline (REF_BL) is driven to ground. The spike-transmission path is driven by the pre-neuronal voltage spike (V_READ), and is active whenever the WRITE_WL is driven low.

Figure 8

(a) Write current required to achieve stochastic potentiation of an MTJ-HM spintronic synapse. The corresponding stochastic STDP dynamics are characterized by a peak switching probability (γ_pot) of 0.15 and a potentiation time constant (τ_pot) of 2 μs. (b) SPICE simulation of the STDP learning circuit, wherein the programming voltage is proportional to the difference in the spike times of pre-neuron and post-neuron pairs. This drives a PMOS operating in saturation to produce a linearly decreasing write current.

Figure 9. Architecture of an SNN composed of excitatory and inhibitory neurons, and arrays of LT-ST stochastic synapses (Bitcell shown in Fig. 7(b)).

The LT synapse is operated at a higher voltage (V_{READ_LT}) than the ST synapse (V_{READ_ST}). The STDP learning circuit (Fig. 7(a)) that is illustrated here is shared by the horizontal array of synapses. The parameters of the learning circuit for the LT and ST synaptic arrays are mentioned in Table 2.

Figure 10

(a) Digit representations learned by arrays of stochastic one-bit synapses connecting the input (28 × 28 pixels) to each of the 400 excitatory neurons. The ratio of the minimum to maximum synaptic conductance is considered to be 1:3. (b) Classification accuracy of the SNN versus the number of excitatory neurons for both the testing and training dataset, with the impact of lateral inhibition reduced during the evaluation phase.

Figure 11

(a) Digit representations learned by arrays of LT-ST synapses connecting the input (28 × 28 pixels) to each of the 400 excitatory neurons. The significant LT synapses contribute to 80% of the total post-synaptic current. (b) Classification accuracy of the SNN versus the number of excitatory neurons for both the proposed synaptic configurations. (c) Programming energy consumption versus the number of excitatory neurons for both the proposed synaptic configurations.