Blueprint for a microwave trapped ion quantum computer

Abstract

The availability of a universal quantum computer may have a fundamental impact on a vast number of research fields and on society as a whole. An increasingly large scientific and industrial community is working toward the realization of such a device. An arbitrarily large quantum computer may best be constructed using a modular approach. We present a blueprint for a trapped ion-based scalable quantum computer module, making it possible to create a scalable quantum computer architecture based on long-wavelength radiation quantum gates. The modules control all operations as stand-alone units, are constructed using silicon microfabrication techniques, and are within reach of current technology. To perform the required quantum computations, the modules make use of long-wavelength radiation-based quantum gate technology. To scale this microwave quantum computer architecture to a large size, we present a fully scalable design that makes use of ion transport between different modules, thereby allowing arbitrarily many modules to be connected to construct a large-scale device. A high error-threshold surface error correction code can be implemented in the proposed architecture to execute fault-tolerant operations. With appropriate adjustments, the proposed modules are also suitable for alternative trapped ion quantum computer architectures, such as schemes using photonic interconnects.

Keywords: Quantum Information Processing; Quantum computing; ion trapping; quantum technology; surface error correction.

Fig. 1. X-junction with multiple zones and corresponding layer structure.

(A) X-junction featuring multiple zones, including a loading zone (marked red) in selected junction. Multiqubit gates are performed after bringing two or more ions (green balls) together in the gate zone (marked green). The gates are performed by applying a static magnetic field gradient produced by current wires placed underneath the electrodes. State readout is carried out in the readout zone (marked blue) using global laser fields and photodetectors placed underneath the electrodes. (B) Layer structure of the ion trap chip consisting of HR silicon substrate and copper current wires embedded in the silicon. Conductive and insulating layers form buried wires, VIAs, through-silicon VIAs (TSVs), and electrodes. (C) Left: Illustration of the rf pseudopotential at the ion height of the proposed optimized X-junction geometry. Right: Remaining rf barrier experienced by the ion when moving through the rf minimum along the z axis. The rf minimum becomes an rf null inside the entanglement region. This simulation was performed for a ¹⁷¹Yb⁺ ion for an ion height of 100 μm and using a drive frequency and voltage of 25 MHz and 200 V, respectively.

Fig. 2. Gradient wires placed underneath each gate zone and embedded silicon photodetector.

(A) Illustration showing an isometric view of the two main gradient wires placed underneath each gate zone. Short wires are placed locally underneath each gate zone to form coils, which compensate for slowly varying magnetic fields and allow for individual addressing. The wire configuration in each zone can be seen in more detail in the inset. (B) Silicon photodetector (marked green) embedded in the silicon substrate, transparent center segmented electrodes, and the possible detection angle are shown. VIA structures are used to prevent optical cross-talk from neighboring readout zones.

Fig. 3. Misaligned modules.

Illustration of two modules misaligned in the xyz axes by 10 μm each (A) and the corresponding rf pseudopotential at the ion height (B). (C) The resulting rf barrier when moving along the rf minimum in the z direction is given in millielectron volt . This simulation was performed for a ¹⁷¹Yb⁺ ion for an ion height of 100 μm and using a drive frequency and voltage of 25 MHz and 200 V, respectively.

Fig. 4. Scalable module illustration.

One module consisting of 36 × 36 junctions placed on the supporting steel frame structure: Nine wafers containing the required DACs and control electronics are placed between the wafer holding 36 × 36 junctions and the microchannel cooler (red layer) providing the cooling. X-Y-Z piezo actuators are placed in the four corners on top of the steel frame, allowing for accurate alignment of the module. Flexible electric wires supply voltages, currents, and control signals to the DACs and control electronics, such as field-programmable gate arrays (FPGAs). Coolant is supplied to the microchannel cooler layer via two flexible steel tubes placed in the center of the modules.

Fig. 5. Illustration of vacuum chambers.

Schematic of octagonal UHV chambers connected together; each chamber is 4.5 × 4.5 m² large and can hold >2.2 million individual X-junctions placed on steel frames.

Fig. 6. Error correction code sequence.

Small section of the scalable architecture illustrating how data and measurement qubits interact with each other in the gate zones to execute the surface code. Data qubits are static, and measurement qubits are shuttled to all adjacent gate zones.