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. 2014 Nov;49(11):2705-2719.
doi: 10.1109/JSSC.2014.2359219.

A 1024-Channel CMOS Microelectrode Array With 26,400 Electrodes for Recording and Stimulation of Electrogenic Cells In Vitro

Affiliations

A 1024-Channel CMOS Microelectrode Array With 26,400 Electrodes for Recording and Stimulation of Electrogenic Cells In Vitro

Marco Ballini et al. IEEE J Solid-State Circuits. 2014 Nov.

Abstract

To advance our understanding of the functioning of neuronal ensembles, systems are needed to enable simultaneous recording from a large number of individual neurons at high spatiotemporal resolution and good signal-to-noise ratio. Moreover, stimulation capability is highly desirable for investigating, for example, plasticity and learning processes. Here, we present a microelectrode array (MEA) system on a single CMOS die for in vitro recording and stimulation. The system incorporates 26,400 platinum electrodes, fabricated by in-house post-processing, over a large sensing area (3.85 × 2.10 mm2) with sub-cellular spatial resolution (pitch of 17.5 μm). Owing to an area and power efficient implementation, we were able to integrate 1024 readout channels on chip to record extracellular signals from a user-specified selection of electrodes. These channels feature noise values of 2.4 μVrms in the action-potential band (300 Hz-10 kHz) and 5.4 μVrms in the local-field-potential band (1 Hz-300 Hz), and provide programmable gain (up to 78 dB) to accommodate various biological preparations. Amplified and filtered signals are digitized by 10 bit parallel single-slope ADCs at 20 kSamples/s. The system also includes 32 stimulation units, which can elicit neural spikes through either current or voltage pulses. The chip consumes only 75 mW in total, which obviates the need of active cooling even for sensitive cell cultures.

Keywords: Extracellular recording and stimulation; high channel count; low noise; low power; microelectrode array (MEA); multirate switched capacitor filter; neural interface; offset compensation; single-slope ADC; switch matrix.

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Figures

Fig. 1
Fig. 1
Diagram of the packaged microelectrode array chip (device concept).
Fig. 2
Fig. 2
System architecture of the CMOS microelectrode array chip.
Fig. 3
Fig. 3
Schematic diagram of a pixel of the electrode array.
Fig. 4
Fig. 4
Diagram of a subset of the switch-matrix. The larger rectangles represent the electrodes; the smaller rectangular dots represent the switches S1 and S2, used to connect the electrodes to the signal wires and to connect the signal wire segments.
Fig. 5
Fig. 5
Schematic of a readout channel. The timing diagram for the multirate SC circuit in the third stage is also shown for different values of the multirate factor (M = 1, 2, 4).
Fig. 6
Fig. 6
Area and power breakdown ofa readout channel. The VGA DAC power contribution is for maximum offset compensation applied. The ADC logic includes the digital latches and output buffers, as well as contributions from shared address decoders.
Fig. 7
Fig. 7
Schematic of the DDA in the Variable-Gain Amplifier. An additional input differential pair is used for offset compensation.
Fig. 8
Fig. 8
Total harmonic distortion of the VGA used in the second stage of the readout. Comparison between the DDA-based implementation, used in this design, and an high-pass filter (HPF) topology using MOS pseudoresistors.
Fig. 9
Fig. 9
Schematic of the shared ramp generator in the ADC.
Fig. 10
Fig. 10
Timing diagram of the single-slope ADC.
Fig. 11
Fig. 11
Schematic of the stimulation unit.
Fig. 12
Fig. 12
Layout of a readout block (32 channels), chip micrograph, close-up view of the electrode array and packaged device. The die size is 7.6 × 10.1 mm2
Fig. 13
Fig. 13
SEM image of the chip surface, showing in-house post-processed Pt-electrodes, plated with rat cortical neurons.
Fig. 14
Fig. 14
Measured frequency response of the amplification chain in the readout channels, for four possible gain settings.
Fig. 15
Fig. 15
Histograms of the gain (at 1 Hz, 10 Hz and 100 Hz) and the low-pass −3 dB cutoff frequency. A nominal gain of 16 × 16 × 4, with a multirate factor M = 2 and fF = 100 kHz, was used for this measurement.
Fig. 16
Fig. 16
Input-referred noise PSD of the full readout chain, including the ADC, with and without electrode contribution.
Fig. 17
Fig. 17
Measured FFT spectrum of one ADC output for an input sine wave at 1.1 kHz.
Fig. 18
Fig. 18
Biphasic stimulation waveforms in voltage and current mode.
Fig. 19
Fig. 19
Acute ex vivo recordings of action potentials from retinal ganglion cells. A raw trace is shown on the left. On the right, a temporal zoom-in of the same trace is shown; recorded measurement values are represented as dots.
Fig. 20
Fig. 20
Data from cortical neurons, cultured on the chip surface for seven days. Left: Spike amplitude map obtained from simultaneous recordings in two regions of interest. Right: Close-up of the area within the red rectangle recorded at maximum spatial resolution; average spike shapes of individual neurons are shown; contour curves used to identify neighboring neurons represent the amplitude of the spike negative peak.
Fig. 21
Fig. 21
Response of a cortical neuron culture to voltage stimulation, recorded at 288 μm from the stimulation electrode. 26 traces of subsequent stimulations and elicited spikes are shown (one trace is shown in black, other traces are in gray).

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