Nanoscale x-ray imaging of circuit features without wafer etching

Abstract

Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules, ideally in a non-destructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions, or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits, with past work delivering 20-40 nm resolution on thinned ICs. We describe a simple model for estimating the required exposure, and use it to estimate the future potential for this technique. Here we show for the first time that this approach can be used to image circuit detail through an unprocessed 300 μm thick silicon wafer, with sub-20 nm detail clearly resolved after mechanical polishing to 240 μm thickness was used to eliminate image contrast caused by Si wafer surface scratches. By using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire non-etched ICs to be imaged to 10 nm resolution or better while maintaining their ability to function in electrical tests.

FIG. 1

Multi-keV x-rays are well suited to image circuit features in whole, unthinned silicon wafers. A plot (a) of the 1/e x-ray attenuation length μ⁻¹ in silicon (Si) as well as in copper (Cu) shows that 10 keV x-rays have reasonable transmission even through 240 μm of Si and 2 μm of Cu. This plot also shows the thickness t_ϕ = λ/(200π|δ_f − δ_b|) through which one obtains a 1/100 radian phase shift difference (detectable in phase contrast imaging methods); this is given for the phase shifting parts of the x-ray refractive index of δ_f for the feature (Cu) and δ_b for the background material (Si), respectively. Finally, the mean free paths for elastic and inelastic scattering of x-rays in silicon are shown at top, indicating that neither multiple elastic scattering nor inelastic scattering should affect image quality through 200–300 μm thick silicon wafers. At bottom (b) is shown an estimate of the number of photons required per resolution element if one is trying to image 20 nm thick copper features in various overall thicknesses of silicon, based on absorption and phase contrast imaging and a signal-to-noise ratio of 5:1. As can be seen, x-ray photon energies of 6–15 keV offer high contrast and sufficient penetration, with 10–15 keV being favored for silicon wafer thicknesses of 200 μm or more.

FIG. 2

X-ray ptychography involves the collection of x-ray diffraction patterns from a scanned, focused coherent beam and their reconstruction to yield an image with a resolution finer than the lens focus. In (d) we show a schematic representation of our experiment, where 10 keV x-rays were produced by an undulator at the Advanced Photon Source (APS) at Argonne, monochromatized using Bragg diffraction from a pair of silicon crystals, and focused by a Fresnel zone plate with a central stop to a 100 nm radius spot. The integrated circuit was scanned across this spot while coherent diffraction patterns were collected on a pixel array detector extending to an angle well beyond the numerical aperture of the Fresnel zone plate. (a) and (b) are the average diffraction patterns from a CMOS chip, and a region of regularly-spaced bit cells in a DRAM chip (see inset of Fig. 5); one can see gaps between active pixel modules in the detector as well as a slight amount of illumination leakage caused by slight misalignment of an order sorting aperture (OSA) placed between the zone plate optic and the specimen (not shown). The azimuthal average power spectrum of the CMOS chip is shown in (c) both from the average of all illuminated pixels, and from two examples of 3 × 3 illumination spots such as might overlap upon one specimen feature during our continuous scanning approach. These power spectra suggest that there is measurable signal at spatial frequencies of about 100 μm⁻¹, corresponding to half-period feature sizes of 5 nm or smaller. This is corroborated in (b) where the annular illumination pupil function is replicated over many diffraction orders from the underlying data bit array periodicity.

FIG. 3

Ptychographic images of a non-production CMOS IC fabricated in 65 nm technology. The image (a) is of this IC as directly removed from its packaging, with a wafer thickness of 300 μm. In this case, the image shows an overlay of features at the chip wiring and gate level, along with variations in the overall wafer thickness which are presumably due to scratches on the surface of the wafer. The image also shows some fringes from out-of-focus features at depth planes far from that of the circuit layer; with a 300 μm separation between the front and back surfaces of the wafer, one would expect these fringes to have a separation scaling like $\sqrt{\lambda z}=193\text{nm}$ which is consistent with what we observe. The image (b) is of a nearby region of the same IC after which it was polished to remove all light-microscope-visible surface scratches; this process reduced the overall wafer thickness to 240 μm but allowed for more straightforward visualization of fine circuit features.

FIG. 4

Light and electron micrographs of a Hynix dynamic random access memory (DRAM) integrated circuit (IC) used for the x-ray ptychographic imaging in Fig. 5. In (a) we show a scanning electron micrograph of a cross-sectional cut into an IC chip; it shows the various metalization layers M1, M2, and M3, as well as the interlayer connection vias V1, V2, and V3. In (b) we show a visible light micrograph of a chip that has undergone a rotation polishing process to remove varying top layers until the bare silicon area was reached (top); the regions imaged using x-ray ptychography (Fig. 5) are indicated with Areas 1, 2, and 3. SEM views of the various layers are shown in (c). Specific features that are also seen in x-ray ptychography (Fig. 5) are indicated with colored markings; the far right area shows Word Lines (WL) and the same area also contains Bit Lines (BL) for addressing specific DRAM storage bit cells.

FIG. 5

Continuous-motion scanning ptychography of a Hynix DRAM integrated circuit using 10 keV x-rays. In (a), we show a region corresponding to Area 1 in the light micrograph of Fig. 4(b), with specific circuit features marked with colored lines to match the equivalent features shown in Fig. 4(c). The region at right shows Word Lines (WL) and Bit Lines (BL) used to address specific DRAM memory bit cells. The reconstruction on Area 2 that only contains thin layers leads to the image (b) of word lines at 64 nm pitch or about 32 nm line width. The line profile across an example Word Line shown in (c) has an edge response (10–90%) of 11.6 nm, suggesting an image resolution of about Δx = 11 nm which is consistent with the diffraction data shown in Fig. 2. Note that the reconstructed optical phase change of about 30 mrad is consistent with the expected phase change of Δφ = 2π(δ_Cu − δ_Si) Δt/λ = 29 mrad for Δt = 50 nm at 10 keV. Image (d) shows the reconstruction from the region corresponding to Area 3 in Fig. 4(b) with individual memory bit cells shown at bottom; the inset shows a refined reconstruction of that subregion (where the diffraction data is shown in Fig. 2(b)) with individual bit cells visible in transmission through the bottom layers of the whole integrated circuit.