Germanium Based Field-Effect Transistors: Challenges and Opportunities

Abstract

The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.

Keywords: buffer; gate stack; germanium; heterogeneous integration; high mobility; passivation; quantum well.

Figure 1.

Hole mobility of Si and Ge as a function of stress and wafer orientation. Ge offers both better intrinsic hole mobility and better scalability compared to Si, reprinted with permission from [20]. Copyright 2012, IEEE.

Figure 2.

Cross-sectional TEM images of heteroepitaxial-Ge layers on Si; (a) 155 nm of Ge grown in single growth cycle with one H anneal step and (b) 400 nm of Ge layer grown in two growth cycles with two H annealing cycles (MHAH method), reprinted with permission from [36]. Copyright 2005, IEEE.

Figure 3.

XTEM micrographs of Ge/Si heteroepitaxy using the ART method. (a,b) Uncoalesced Ge grown by epitaxial lateral overgrowth (ELO) from a single trench (indicated by a black arrow). The surface has been flattened using CMP; (c) ART Ge/Si in which growth from adjacent overgrown trenches has coalesced, reprinted with permission from [42]. Copyright 2009, The Electrochemical Society.

Figure 4.

HRTEM image of Ge grown on SHO. The interface between Ge and SHO is atomically sharp and contains no interfacial layer (inset), reprinted with permission from [46]. Copyright 2007, Elsevier.

Figure 5.

HRTEM images of Ge-rich SiGe layer produced by the Ge condensation technique. The Ge composition is 89%, reprinted with permission from [65]. Copyright 2009, Elsevier.

Figure 6.

Calculated band offsets of oxides on Ge, reprinted with permission from [97]. Copyright 2013, AIP Publishing LLC.

Figure 7.

(a) Thicknesses of GeO_x ILs with different Al₂O₃ thicknesses and plasma powers; (b) D_it of Au/Al₂O₃/GeO_x/Ge MOS capacitors as a function of the GeO_x IL thickness. The D_it reported is for 0.2 eV above the valence band, reprinted with permission from [14]. Copyright 2012, IEEE.

Figure 8.

(a) Cross-sectional TEM image of a high-k metal gate stack with a thin Si cap on a Ge QWFET. Part of the Si cap is oxidized due to thermal cycles during the transistor fabrication process; (b) Capacitance-voltage characteristics of Ge pQWFETs with different Si cap thicknesses, reprinted with permission from [15]. Copyright 2010, IEEE.

Figure 9.

Room temperature hole mobility vs. sheet carrier density in biaxially compressed QWs: InSb [157,158], In_0.4Ga_0.6Sb, In_0.35Ga_0.65As [189,190], In_0.83Ga_0.17As [191], Ge [,–197].

Figure 10.

Effective mass vs. sheet carrier density in biaxially compressed QWs.

Figure 11.

Device research vehicle for Ge on Si for low-power logic, and comparison of MOSFET, QWFET, and MOS-QWFET structures.

Figure 12.

(a) Cross-sectional TEM micrograph of a 65 nm Ge- pMOSFET, reprinted with permission from [10]. Copyright 2008, IEEE; (b) Cross-sectional TEM micrograph of a Ge pQWFET, reprinted with permission from [15]. Copyright 2010, IEEE. Note the raised source/drain (RSD) in the QWFET which allows for reduction/removal of the S/D implantation.

Figure 13.

Transfer characteristics of measured (a) 65 nm Ge pMOSFET at low and high V_DS with superior reproducibility, reprinted with permission from [10]. Copyright 2008, IEEE; (b) 100 nm Ge pQWFET at VDS = −0.05 V (open circle) and −0.5 V (solid circle). The device exhibits a subthreshold slope (SS) of 97 mV/dec enabled by the phosphorus junction layer underneath the channel, which suppresses parallel conduction through the SiGe buffer, reprinted with permission from [15]. Copyright 2010, IEEE.

Figure 14.

Benchmarking relation (I_off vs. I_dsat) of 65 nm Ge pMOSFET, 40 nm InSb QWFET and 100 nm Ge QWFET at a supply voltage of 0.5 V. The Ge QWFET demonstrated the highest ON current at a given OFF-state leakage current, reprinted with permission from [2]. Copyright 2011, Nature Publishing Group.

Figure 15.

Schematic of extremely-high mobility NMOS and PMOS co-integrated for complete CMOS heterogeneously integrated on Si.