Recent Progress of Ferroelectric-Gate Field-Effect Transistors and Applications to Nonvolatile Logic and FeNAND Flash Memory

Abstract

We have investigated ferroelectric-gate field-effect transistors (FeFETs) with Pt/SrBi₂Ta₂O₉/(HfO₂)_x(Al₂O₃)_1-x (Hf-Al-O) and Pt/SrBi₂Ta₂O₉/HfO₂ gate stacks. The fabricated FeFETs have excellent data retention characteristics: The drain current ratio between the on- and off-states of a FeFET was more than 2 × 10⁶ after 12 days, and the decreasing rate of this ratio was so small that the extrapolated drain current ratio after 10 years is larger than 1 × 10⁵. A fabricated self-aligned gate Pt/SrBi₂Ta₂O₉/Hf-Al-O/Si FET revealed a sufficiently large drain current ratio of 2.4 × 10⁵ after 33.5 day, which is 6.5 × 10⁴ after 10 years by extrapolation. The developed FeFETs also revealed stable retention characteristics at an elevated temperature up to 120 °C and had small transistor threshold voltage (V_th) distribution. The V_th can be adjusted by controlling channel impurity densities for both n-channel and p-channel FeFETs. These performances are now suitable to integrated circuit application with nonvolatile functions. Fundamental properties for the applications to ferroelectric-CMOS nonvolatile logic-circuits and to ferroelectric-NAND flash memories are demonstrated.

Keywords: FeFET; nonvolatile logic; nonvolatile memory; semiconductor memory.

Figure 1

Schematic cross section of a fabricated FeFET. Gate, ferroelectric and insulator are made of Pt, SBT and Hf-Al-O, respectively. Reprinted from [17] with permission of the Japan Society of Applied Physics.

Figure 2

Drain current-gate voltage curves of an n-channel Pt/SBT/Hf-Al-O/Si FeFET at V_g = ±6.0 V. The inset was made by measuring the curves at V_g = ±4.0, ±5.0, ±6.0, ±7.0 and ±8.0 V. Scan voltage is each gate-voltage amplitude applied to the FeFET. The almost linearly increasing memory window shown in the inset indicates that ferroelectric polarization in the FeFET is not saturated even at V_g = ±8.0 V. Reproduced from [15] with permission of IEEE.

Figure 3

Drain current retention of a Pt/SBT/Hf-Al-O/Si FeFET. Potential 10 year retention is indicated by the extension lines on the measured retention curves. Modified from [15].

Figure 4

Pulse endurance property of a Pt/SBT/Hf-Al-O/Si FeFET. The inset shows a cycle of the gate voltages which were periodically applied. Reprinted from [15] with permission of IEEE.

Figure 5

(a) Cross-sectional view of a gate by TEM, reprinted from reference [17] with permission of the Japan Society of Applied Physics, and (b) a gate-leakage property of Pt/SBT/Hf-Al-O/Si FeFETs, reprinted from reference [15] with permission of IEEE.

Figure 6

(a) Self-aligned-gate process for fabricating FeFETs; (b) Drain current retention of a self-aligned-gate Pt/SBT/Hf-Al-O/Si FeFET with L = 2µm. Respective curves for on- and off-states were measured over one month. Thicknesses of the SBT and Hf-Al-O were 420 nm and 12 nm. Modified from [28].

Figure 7

Electrical properties of FeFETs measured at elevated temperatures. (a) Drain current-gate voltage curves, and (b) the drain current retentions of a p-channel Pt/SBT/Hf-Al-O/Si FeFET. Thicknesses of the SBT and Hf-Al-O were 600 nm and 7 nm. Reprinted from [30] with permission of the American Institute of Physics. Good stability of FeFET data retention even at 120 °C was also supported by measuring the retentions of an n-channel Pt/SBT/HfO₂/SiON/Si FeFET (c). Thicknesses of the SBT and HfO₂ were 450 nm and 6 nm. Reprinted from [31] with permission of IOP Publishing Ltd.

Figure 7

Electrical properties of FeFETs measured at elevated temperatures. (a) Drain current-gate voltage curves, and (b) the drain current retentions of a p-channel Pt/SBT/Hf-Al-O/Si FeFET. Thicknesses of the SBT and Hf-Al-O were 600 nm and 7 nm. Reprinted from [30] with permission of the American Institute of Physics. Good stability of FeFET data retention even at 120 °C was also supported by measuring the retentions of an n-channel Pt/SBT/HfO₂/SiON/Si FeFET (c). Thicknesses of the SBT and HfO₂ were 450 nm and 6 nm. Reprinted from [31] with permission of IOP Publishing Ltd.

Figure 8

(a) Drain current-gate voltage curves of 94 n-channel Pt/SBT/Hf-Al-O/Si FeFETs and (b) V_th distribution of the 94 n-channel FeFETs; (c) Drain current-gate voltage curves of 95 p-channel Pt/SBT/Hf-Al-O/Si FeFETs and (d) V_th distribution of the 95 p-channel FeFETs. Thicknesses of the SBT and Hf-Al-O were 400 nm and 7 nm. Reprinted from reference [32] with permission of IOP Publishing Ltd.

Figure 9

(a) Schema explaining nonvolatile logic operation of the FeCMOS inverter; (b) Demonstrations of operational switching between logic and memory mode of the FeCMOS inverte; (c) V_out-data retention with nondestructive readout. Reproduced from [37] with permission of the Institution of Engineering and Technology.

Figure 10

(a) Microscopic photo and (b) measured retention with nondestructive readout of double-stage FeCMOS inverter circuit. Reproduced from [38] with permission of IEICE.

Figure 11

Program/erase endurance characteristics up to 10⁸ cycles of a FeNAND memory cell. Reproduced from [41] with permission of IEEE.

Figure 12

Data retention after the program, erase, V_pgm disturb and V_pass disturbs. Reproduced from [41] with permission of IEEE.

Figure 13

(a) Equivalent circuit of a 4 × 2 FeNAND memory cell array and (b) distribution of accumulated bit-line currents of 51 programmed patterns, which were measured every time after an erase-and-program cycle. Reproduced from [42] with permission of IOP Publishing Ltd.