A novel true random number generator based on a stochastic diffusive memristor

Abstract

The intrinsic variability of switching behavior in memristors has been a major obstacle to their adoption as the next generation of universal memory. On the other hand, this natural stochasticity can be valuable for hardware security applications. Here we propose and demonstrate a novel true random number generator utilizing the stochastic delay time of threshold switching in a Ag:SiO₂ diffusive memristor, which exhibits evident advantages in scalability, circuit complexity, and power consumption. The random bits generated by the diffusive memristor true random number generator pass all 15 NIST randomness tests without any post-processing, a first for memristive-switching true random number generators. Based on nanoparticle dynamic simulation and analytical estimates, we attribute the stochasticity in delay time to the probabilistic process by which Ag particles detach from a Ag reservoir. This work paves the way for memristors in hardware security applications for the era of the Internet of Things.Memristors can switch between high and low electrical-resistance states, but the switching behaviour can be unpredictable. Here, the authors harness this unpredictability to develop a memristor-based true random number generator that uses the stochastic delay time of threshold switching.

Fig. 1

Stochastic threshold switching behavior in a Ag:SiO₂ based diffusive memristor. a Optical microscopic image of the 5 × 5 µm² Ag:SiO₂ cross-point device. Scale bar, 50 µm. Inset shows geometry of the Ag:SiO₂ diffusive memristor. Note that a 5 nm Ag layer is inserted between switching layer and top electrode to provide enough Ag supply. b 50 Consecutive DC switching cycles of the diffusive memristor connected to a 4.7 MΩ series resistor. c Typical pulse switching behavior of the diffusive memristor. Under a voltage pulse (300 µs in this case), some delay time is needed before the device abruptly turns ON. Inset shows the circuit for the measurements with a 120 kΩ resistor connected in series to the memristor. d Distribution of delay time for different input pulse amplitude (0.4 to 0.9 V at 50 Hz). A higher voltage leads to a shorter average delay time with a narrower distribution

Fig. 2

Working principle of a diffusive memristor based true random number generator (TRNG). a Circuit diagram of a TRNG with a diffusive memristor, a comparator (CMP), an AND gate, and a counter. b Schematic pulse waveforms at each stage of the circuit (as labeled in a), illustrating the working principle of our diffusive memristor TRNG. The stochastic delay time of the diffusive memristor leads to variations of the pulse width (shown in 3) and then random numbers of clock pulses that are sent to the counter (shown in 5). The bit status (counter output) before, during and after flipping is labeled in red in 6. The bit flipping is triggered by the rising edge of clock signal and hence the bit flipping frequency is half of the clock frequency. The counter output is random due to the random times of bit flipping, as determined by the random numbers of clock pulses sent to the counter (V ₅)

Fig. 3

Experimental demonstration of a diffusive memristor true random number generator. a Photo of our simple circuit built on a breadboard. b Monitored one counter output in response to input voltage pulse (1 kHz) applied on our diffusive memristor. c Monitored one random binary output flipping from “1” → “0” → “0” → “1” → “0” over continuous switching cycles

Fig. 4

Physical origin of stochastic delay time clarified by nanoparticle dynamics simulations. a The switching of the simulated memristor conductance when 48 rectangular voltage pulses are applied, with conductance normalized by the maximum memristor conductance, and b the variation of voltage across the memristor, normalized by the threshold voltage V _th. c The switching to the low resistive state at time measured from the beginning of the corresponding pulses. The randomness of the resistive switching is clearly seen. d The two chosen resistive switches with different delay time and e corresponding particle probability distributions (1–18) marked on d by yellow points. Inset in d shows the circuit model used during the simulation. The memristor is connected with a parallel capacitor and a series resistor. f Potential normalized by thermal fluctuations across the sample used here. The delay time is composed of charging time of capacitor, time of Ag particles detach from Ag reservoir and the Ag transportation time until the formation of conduction channel(s), while the stochasticity is mainly attributed to the stochastic detaching process. For simulations in a–e, we used the following voltage pulse parameters: voltage pulse duration κt _p = 80 (allowing enough time to switch to low resistive state for every pulse), inter-pulse interval κΔt = 360 (allowing enough times to relax) and voltage amplitude V _am/V _th = 1.6, potential versus temperature as in f (all times measured in unit of thermal relaxation time 1/κ). The experimental delay time distributions under (g) 0.4 V and (h) 0.7 V fitted by eq. 2. i The fitting curve of t ₀ vs. pulse amplitudes according to eq. (3). The fitted probability distributions appear to be consistent with experimental results, confirming the feasibility of our proposed mechanism