SNDR Limits of Oscillator-Based Sensor Readout Circuits

Abstract

This paper analyzes the influence of phase noise and distortion on the performance of oscillator-based sensor data acquisition systems. Circuit noise inherent to the oscillator circuit manifests as phase noise and limits the SNR. Moreover, oscillator nonlinearity generates distortion for large input signals. Phase noise analysis of oscillators is well known in the literature, but the relationship between phase noise and the SNR of an oscillator-based sensor is not straightforward. This paper proposes a model to estimate the influence of phase noise in the performance of an oscillator-based system by reflecting the phase noise to the oscillator input. The proposed model is based on periodic steady-state analysis tools to predict the SNR of the oscillator. The accuracy of this model has been validated by both simulation and experiment in a 130 nm CMOS prototype. We also propose a method to estimate the SNDR and the dynamic range of an oscillator-based readout circuit that improves by more than one order of magnitude the simulation time compared to standard time domain simulations. This speed up enables the optimization and verification of this kind of systems with iterative algorithms.

Keywords: Sigma-Delta modulation; VCO-ADC; oscillator-based sensor; phase noise; time-domain circuits.

Figure 1

Example of two oscillator-based sensor readout circuits. The sensing element can be integrated into the oscillator (a) or can be connected to an analog interface that generates an intermediate signal $v_{in}$ that modulates the oscillator (b). In both cases, the input measurand $x\left(t\right)$ modulates the frequency of the oscillation $v\left(t\right)$ (c).

Figure 2

Effects of noise in the spectra of a VCO-ADC. (a) Spectrum of $v\left(t\right)$; (b) Spectrum of the output of the converter $y\left[n\right]$ assuming a sinusoidal input.

Figure 3

Classical approach to estimate the influence of phase noise in the performance of first-order VCO-ADCs.

Figure 4

Generic high-order oscillator-based $\mathrm{\Sigma }\mathsf{\Delta }$ modulator.

Figure 5

Spectrum of the oscillation around the center frequency.

Figure 6

Simplified representation of $\mathcal{L}\left(f\right)$ commonly used at low and middle offset frequencies. Definitions (1) and (2) differ at very low offset frequencies.

Figure 7

(a) Diagram of a real VCO with phase noise added to the phase of the oscillator; (b) Equivalent block diagram of the VCO with the phase noise referred to the input.

Figure 8

XOR-based VCO-ADC.

Figure 9

(a) Power spectrum of the oscillation $S_v\left(f\right)$; (b) Phase noise and phase fluctuation power spectral density; (c) IRPN and output data power spectral density.

Figure 10

130 nm CMOS prototype description. (a) Circuit; (b) Die micrograph.

Figure 11

Measured oscillation frequency vs. input voltage.

Figure 12

Test fixture for phase noise measurements.

Figure 13

(a) $S_v\left(f\right)$ measured with an spectrum analyzer; (b) Phase noise derived from $S_v\left(f\right)$; (c) Comparison between the IRPN calculated from $\mathcal{L}\left(\mathsf{\Delta }f\right)$ and the DFT of the measured ADC output.

Figure 14

Power spectrum of the ADC output.

Figure 15

Simulated voltage-controlled ring oscillator.

Figure 16

Comparison between different periodic noise simulations.

Figure 17

(a) Performance of circuit shown in Figure 15 calculated using transient simulations and estimated from PSS and Pnoise simulations; (b) SNDR difference between both methodologies.