In-situ, In-Memory Stateful Vector Logic Operations based on Voltage Controlled Magnetic Anisotropy

Abstract

Recently, the exponential increase in compute requirements demanded by emerging applications like artificial intelligence, Internet of things, etc. have rendered the state-of-art von-Neumann machines inefficient in terms of energy and throughput owing to the well-known von-Neumann bottleneck. A promising approach to mitigate the bottleneck is to do computations as close to the memory units as possible. One extreme possibility is to do in-situ Boolean logic computations by using stateful devices. Stateful devices are those that can act both as a compute engine and storage device, simultaneously. We propose such stateful, vector, in-memory operations using voltage controlled magnetic anisotropy (VCMA) effect in magnetic tunnel junctions (MTJ). Our proposal is based on the well known manufacturable 1-transistor - 1-MTJ bit-cell and does not require any modifications in the bit-cell circuit or the magnetic device. Instead, we leverage the very physics of the VCMA effect to enable stateful computations. Specifically, we exploit the voltage asymmetry of the VCMA effect to construct stateful IMP (implication) gate and use the precessional switching dynamics of the VCMA devices to propose a massively parallel NOT operation. Further, we show that other gates like AND, OR, NAND, NOR, NIMP (complement of implication) can be implemented using multi-cycle operations.

Figure 1

(a) A VCMA based MTJ. The MTJ consists of a pinned layer and a free layer separated by a non-magnetic spacer. When a voltage is applied across the MTJ, there is a redistribution of electrons in the d-orbitals thus making the interface anisotropy sensitive to the applied voltage. (b) Schematic representation of the voltage asymmetry of the VCMA based MTJs. When a positive (negative) voltage is applied across the VCMA MTJ the energy barrier (EB) decreases (increases) due to the lowering (enhancement) of the interface anisotropy. Thus, VCMA mechanism makes the MTJ asymmetric with respect to voltage polarity, a positive voltage assists in switching the MTJ whereas a negative voltage makes it much harder to switch the MTJ. (c) Figure representing the precessional switching mechanism. When a positive voltage is applied across the MTJ such that the interface anisotropy is sufficiently lowered, the magnetization vector becomes free to precess around the hard axis due to the effective in-plane field (H_in−_plane). Inset shows the lowering of the interface anisotropy on application of sufficiently high positive voltage (V > 0). While the magnetization vector is precessing around the hard-axis, if the voltage pulse is switched OFF when the magnetization is close to point A, it would slowly dampen towards −z direction, thereby switching the direction of magnetization by 180°. A voltage pulse as a function of time marked with the points corresponding to the state of magnetization vector at a particular time instance is also shown in the figure.

Figure 2

(a) The NEGF based MTJ-resistance model benchmarked against experimental data from. (b) A graphical representation of the various components of our self-consistent magnetization dynamics and resistance transport model.

Figure 3

(a) The truth table for two input IMP operation. The columns B and B’ are the same except for row 1, highlighted in red. (b) The array configuration showing the voltages at various SLs and WLs and the current flow during the stateful computation of the bit-wise IMP operation. (c) A simplified circuit showing the voltage divider configuration resulting due to the applied voltages at the SLs and WLs. (d) A typical magnetization dynamics during the switching of the MTJ-2 from the P to the AP state, when MTJ-1 is in the P state. Note, this switching dynamics is a typical STT dominated switching, VCMA effect lowers the EB for MTJ-2, thereby allowing the small current flowing through the MTJ-2 to be able to selectively switch the MTJ-2 as desired. (e) Figure showing the magnetization component m_z for all the four cases of the truth table shown in (a).

Figure 4

(a) The truth table for NOT operation. (b) The array configuration showing the voltages at various BLs and WLs and the current flow during the stateful computation of the massively parallel NOT operation. (c) A typical magnetization dynamics showing the precessional switching behavior of the VCMA MTJs mimicking the NOT operation. On application of proper voltages, irrespective of the initial state of the magnetization direction (+z or −z), the magnetization vector switches by 180° thereby implementing the desired stateful NOT operation.

Figure 5

Based on the proposed stateful operations as described in the above sub-sections an IMP and NOT operation can be completed in one cycle, whereas a two cycle operation can implement the NAND, NIMP and OR logic. Similarly, a three cycle operation can be used for the AND and NOR logic computation. For multi-cycle logic, the part of logic highlighted in red can be computed in the first cycle, the part in white can be computed in second cycle, while the part highlighted in blue would be computed in the third cycle.

Figure 6

(a) Probability of B’s final state being ‘H’ (or digital ‘1’) for the four initial cases of A and B (00, 01, 10, 11) in the vector IMP operation, as a function of the voltage pulse. At a pulse width of ~25 ns, the correct IMP result is obtained. (b) Probability of inverting the state of the VCMA MTJ due to precessional switching as a function of the pulse duration. The switching probability peaks at ~2 ns due to the half-cycle rotation of the magnetization dynamics.

Figure 7

(a) A truth table for XOR gate. The logic output B’ retains its original value when the operand A is ‘L’, whereas if the operand A is ‘H’, the new value for B’ is the complement of its original value B. (b) Figure shows the array structure used for implementing the XOR operation. The voltages on BLs represent the bits corresponding to the operand A, while the data stored in the MTJs represent the bits corresponding to the operand B. The values in the MTJs are inverted conditionally only if the bits corresponding to the operand A are ‘H’ i.e. only if the respective SLs are pulled high. Note, in the example shown, the bit value for A₁ is ‘L’, as such, BL-1 is kept low. Therefore, no current flows through the column corresponding to BL-1 and hence the bits corresponding to BL-1 consume no energy.