High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures

Abstract

2D layered materials (2DLMs), together with their heterostructures, have been attracting tremendous research interest in recent years because of their unique physical and electrical properties. A variety of circuit elements have been made using mechanically exfoliated 2DLMs recently, including hard drives, detectors, sensors, and complementary metal oxide semiconductor field-effect transistors. However, 2DLM-based amplifier circuit elements are rarely studied. Here, the integration of 2DLMs with 3D bulk materials to fabricate vertical junction transistors with current amplification based on a MoS₂/GaTe heterostructure is reported. Vertical junction transistors exhibit the typical current amplification characteristics of conventional bulk bipolar junction transistors while having good current transmission coefficients (α ∼ 0.95) and current gain coefficient (β ∼ 7) at room temperature. The devices provide new attractive prospects in the investigation of 2DLM-based integrated circuits based on amplifier circuits.

Keywords: 2D materials; bipolar junction transistor; current amplification; van der Waals heterostructure.

Figure 1

Schematic diagram showing fabrication process flow of the vertical bipolar junction transistor.

Figure 2

a) The optical microscopy of the bipolar junction transistor device showing the base and emitter contacts. Scale bar: 10 µm. b) Schematic diagram of the structure for the bipolar junction transistor. c) Typical photoluminescence spectra of an individual MoS₂, an individual GaTe and a MoS₂/GaTe heterostructure. d,e) Height profiles of the device. A step height of GaTe ≈100 nm and MoS₂ ≈8 nm is measured. Inset: AFM image of the device. g,h) Spatially resolved Raman maps for the GaTe (Raman shift at 145 cm⁻¹) and the MoS₂ (Raman shift at 408 cm⁻¹). f) Cross‐sectional TEM images of the device. Scale bar is 2 nm. i) EDS mapping of the device.

Figure 3

Current versus bias voltage characteristic of a) MoS₂/p‐Si junction and b) GaTe/MoS₂ junction. The insets show the measurement schematic diagrams for p‐silicon/MoS₂ and GaTe/MoS₂ junction, respectively.

Figure 4

a) Measured forward common‐base output characteristics (I _C ‐V _CB) with a step size I _E from 0 µA to 14 µA. b) The common‐base current gain (α) versus base–collector voltage (V _CB) curves at room temperature. c). Base–collector junction is punctured through when further increasing V _CB after saturation region.

Figure 5

a) Measured forward common‐emitter output characteristics (I _C ‐V _CE) with a step size I _B from 0 to 400 nA. b) The common‐emitter current gain (β) versus collector–emitter voltage (V _CE) curves at room temperature.

Figure 6

Band diagrams along the vertical dashed line in Figure 2b are shown in original state a), common‐base configuration (amplification state) b), common‐emitter configuration (saturation state) c), respectively.