CMOS MEMS Fabrication Technologies and Devices

Abstract

This paper reviews CMOS (complementary metal-oxide-semiconductor) MEMS (micro-electro-mechanical systems) fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator) CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

Keywords: CMOS (complementary metal-oxide-semiconductor); CMOS MEMS; MEMS (micro-electro-mechanical systems); actuators; integration; sensors.

Figure 1

Cross-section of CMOS (complementary metal-oxide-semiconductor) and MEMS micro-electro-mechanical systems) in the recess trench in pre-CMOS integration [12].

Figure 2

Die photo of a 3-axis accelerometer implemented by iMEMS processes [13].

Figure 3

Die photo of an integrated gyroscope by Analog Devices [15].

Figure 4

Schematic of two digital mirror device (DMD) mirror-pixels in a digital light processing (DLP) cinema chip (a) and scanning electron microscope (SEM) image of an array of DMD micromirrors (b). From www.dlp.com.

Figure 5

Illustrative structure and circuits of the radio frequency (RF) switch in [40] (a), and SEM photograph of the chip (b).

Figure 6

Dry-etching-based post-CMOS fabrication process for MEMS structures made of CMOS thin films [57]. (a) CMOS wafer or die; (b) SiO₂ etching; (c) Silicon deep reactive ion etching (DRIE); (d) Silicon reactive ion etching (RIE) with lateral undercut.

Figure 7

Die photo and SEM image of an integrated convective accelerometer from MEMSIC [68].

Figure 8

DRIE bulk CMOS-MEMS process flow for 4-metal-layer CMOS [70]. (a) Backside silicon DRIE to define MEMS areas; (b) Front SiO₂ etching; (c) Front-side silicon DRIE; (d) Front-side RIE with lateral undercut.

Figure 9

SEM images and structure illustration of an electro-thermal micromirror by bulk post-CMOS microfabrication [71]. (a) Micrographs of the mirror and microstructures; (b) Illustrative composition of the mirror structures.

Figure 10

Modified bulk CMOS MEMS process for separate etching of CMOS beams and single crystal silicon (SCS) microstructures [75]. (a) Backside silicon DRIE; (b) Thermal protection using photoresist (PR); (c) Front-side SiO₂ etching; (d) Front-side silicon DRIE for beams; (e) Front-side silicon DRIE for comb drives; (f) Removal of thermal protection PR layer.

Figure 11

Die photo (a) and SEM micrograph of microstructures in the sensor (b) reported in [76].