Three-dimensional monolithic integration in flexible printed organic transistors

Abstract

Direct printing of thin-film transistors has enormous potential for ubiquitous and lightweight wearable electronic applications. However, advances in printed integrated circuits remain very rare. Here we present a three-dimensional (3D) integration approach to achieve technology scaling in printed transistor density, analogous to Moore's law driven by lithography, as well as enhancing device performance. To provide a proof of principle for the approach, we demonstrate the scalable 3D integration of dual-gate organic transistors on plastic foil by printing with high yield, uniformity, and year-long stability. In addition, the 3D stacking of three complementary transistors enables us to propose a programmable 3D logic array as a new route to design printed flexible digital circuitry essential for the emerging applications. The 3D monolithic integration strategy demonstrated here is applicable to other emerging printable materials, such as carbon nanotubes, oxide semiconductors and 2D semiconducting materials.

Fig. 1

3D monolithic integration in flexible printed transistors. a, b Printed single-gate and dual-gate organic transistors. c, d 3D-integrated two (n-/p-type, stacked 2-T) and three (n-/p-/n-type, stacked 3-T) complementary dual-gate organic transistors with shared gate electrodes. All the films were printed except for the Parylene dielectric layers

Fig. 2

Images of a stacked 3-T device. a Sequential images of the process of printing seven metal layers (scale bar is 1 mm). b A polarized microscopy image of the transistor area (scale bar is 200 μm). c A topographic AFM image (scan area is 100 × 100 μm) measured on top of the channel area. The inset graph shows the profile along the cross-section line. d Cross-sectional SEM image of the stacked 3-T device (M1-7: metal layers, GI1-6: dielectric insulator layers, OSC1-3: organic semiconductor layers, scale bar is 250 nm, Pt was sputtered on the top prior to the SEM measurement)

Fig. 3

Device characteristics. a |I_D|–V_GS transfer characteristics of the n-type and p-type organic transistors in single-gate (bottom-gate and top-gate) and dual-gate configurations. b The subthreshold swings and c the I_D on-off ratios. d The extracted carrier mobilities in the 3D-integrated complementary organic transistors. e The channel length dependency of the extracted carrier mobilities. Error bars represent standard deviation

Fig. 4

Dual-gate complementary transistor operations. a Saturation transfer characteristics (V_DS = 5 V) of the n-type dual-gate transistor in top-gate (left) and bottom-gate (right) sweeping modes (V_TG: top-gate voltage, V_BG: bottom-gate voltage). b Saturation transfer characteristics (V_DS = −5 V) of the p-type dual-gate transistor in top-gate (left) and bottom-gate (right) modes

Fig. 5

Stacked 2-T dual-gate devices. a Schematic circuit of the 3D-integrated dual-gate inverter (V_G1, V_G2, V_G3: gate inputs, I_DD: static current from the source). b Voltage transfer characteristics (left) and static currents (right) of the inverter operation according to the combinations of electrical gate connections. c Schematic circuit of the ring oscillator which is composed of seven 3D-integrated dual-gate inverters and its oscillation operation. The buffer output stage consists of serially connected two inverters, where the transistor W of the last inverter is designed to be eight times larger than that of the others

Fig. 6

3D NAND digital circuit design based on stacked 3-T dual-gate devices. a Schematic circuits of a conventional NAND gate and a proposed 3D NAND gate. b DC V_OUT–V_IN characteristics of a 3D NAND gate. c 3D NAND array-based logic design (scale bar is 2 mm). d DC V_IN–V_OUT characteristics of a 1-input NOT gate and 2-input (A and B) logic gates (OR, AND, NOR, XOR, and XNOR) implemented by interconnecting 3D NANDs. A fixed voltage (0 or 5 V) is applied to one port while a voltage input on the other port is swept. e A large-scale flexible logic circuitry implemented by using a 12 × 8 3D NAND gate array (scale bar is 4 mm)

Fig. 7

Transistor density trend of printed organic circuits fabricated by various printing techniques

Fig. 8

Mechanical, electrical, long-term, and environmental reliabilities a Images of the stacked 3-T device under bending test (white dotted area is magnified) and its saturation transfer characteristics as bent on a curved surface (scale bars in the top and bottom images are 1 cm and 1 mm, respectively). b Shift of the saturation transfer characteristics of the printed stand-alone complementary transistors after electrical bias stress for 10,000 s (at V_GS = V_DS = 5 V for the n-type and −5 V for the p-type). c Year-long observation on the carrier mobilities and threshold voltages of the stand-alone and stacked 2-T devices (μ_n, μ_p: carrier mobility, μ_n0, μ_p0: initial carrier mobility, V_TH,n, V_TH,p: threshold voltage, error bars represent standard deviation). d Shift of the saturation transfer characteristics of the complementary dual-gate transistors under consecutive five thermal stress steps. e Shift of the saturation transfer characteristics of the complementary dual-gate transistors under a humid environment (90% rh, 30 °C) for 24 h (rh: relative humidity)