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. 2019 Feb 12:13:1.
doi: 10.3389/fncom.2019.00001. eCollection 2019.

Symbolic Modeling of Asynchronous Neural Dynamics Reveals Potential Synchronous Roots for the Emergence of Awareness

Pierre Bonzon  1
Affiliations

Symbolic Modeling of Asynchronous Neural Dynamics Reveals Potential Synchronous Roots for the Emergence of Awareness

Pierre Bonzon. Front Comput Neurosci. .

Abstract

A new computational framework implementing asynchronous neural dynamics is used to address the duality between synchronous vs. asynchronous processes, and their possible relation to conscious vs. unconscious behaviors. Extending previous results on modeling the first three levels of animal awareness, this formalism is used here to produce the execution traces of parallel threads that implement these models. Running simulations demonstrate how sensory stimuli associated with a population of excitatory neurons inhibit in turn other neural assemblies i.e., a kind of neuronal asynchronous wiring/unwiring process that is reflected in the progressive trimming of execution traces. Whereas, reactive behaviors relying on configural learning produce vanishing traces, the learning of a rule and its later application produce persistent traces revealing potential synchronous roots of animal awareness. In contrast, to previous formalisms that use analytical and/or statistical methods to search for patterns existing in a brain, this new framework proposes a tool for studying the emergence of brain structures that might be associated with higher level cognitive capabilities.

Keywords: asynchronous process; emergence of awareness; neural dynamics; symbolic modeling; synchronous process.

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Figures

Figure 1
Figure 1
Circuit fragment implementing a synaptic transmission.
Figure 2
Figure 2
Thread patterns for a synaptic transmission.
Figure 3
Figure 3
Communication protocol for an asynchronous communication.
Figure 4
Figure 4
A mesoscale virtual circuit implementing classical conditioning.
Figure 5
Figure 5
Micro-circuit and communication protocol for ltp.
Figure 6
Figure 6
A virtual circuit implementing simple operant conditioning.
Figure 7
Figure 7
High level definition of a virtual machine run.
Figure 8
Figure 8
Circuit for configural learning.
Figure 9
Figure 9
Execution trace. (A–C) Transient part. (D,E) Void part.
Figure 10
Figure 10
Circuit for rule learning.
Figure 11
Figure 11
Execution trace. (A–D) Transient part. (E,F) Persistent part.
See this image and copyright information in PMC

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