Miniaturization of CMOS

Abstract

When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today's 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

Keywords: CMOS; FinFETs; device processing; integrated circuits.

Figure 1

Miniaturization of the transistor gate length in different technology nodes and production years [22].

Figure 2

A schematic drawing of MOSFET downscaling [23].

Figure 3

Normalized cost/layer vs. lithography method.

Figure 4

Evolution of the lithography technique where the pattern becomes denser and smaller in each new technology node. To prevent pattern collapse, the thickness of resist is reduced proportionally to the minimum half-pitch (HP) of lines/spaces.

Figure 5

Process flow for the bulk FinFETs or planar transistors. The FinFETs process are underlined [36].

Figure 6

(a) Parasitic resistances and (b) capacitances in each technology node [22].

Figure 7

Values of contacted CD for advanced device.

Figure 8

New challenges in the miniaturization of FinFETs [36].

Figure 9

Ge contents in S/D for different technology nodes.

Figure 10

(a) Si fin covered with SiO₂ (b) removal of Si in the fin after wet-etch by TMAH and (c) HCl vapor etch [61].

Figure 11

Cross-section TEM of strained Ge-cap/ SRB Si_0.3Ge_0.7 grown in an oxide trench and observed at (a) fin cut and (b) along the trench. The Si was removed by the wet etch prior to epitaxy [62].

Figure 12

HRSEM of a multilayer of the SiGe/Si structure with eight periods [66].

Figure 13

Schematic of the monolayer doping process [70].

Figure 14

Cross-sectional SEM images of W films grown in different conditions: (a) on blank wafers and (b) trenches filling capacity [104].

Figure 15

XRD spectra of ALD W using SiH₄ and B₂H₆ and calculated stress data on a blank substrate [98].

Figure 16

(a) Electron effective mobility in NFET and (b) TEM images Ω-Gate CMOS NW transistors for N-FET [108].

Figure 17

Tensile stress change with a UV cure.

Figure 18

(a) Schematic picture of a stack of Si_0.75Ge_0.25/Si NW used for selective etch and TEM across a section of 30-nm wide Si-Si_0.75Ge_0.25 NWs after Si selectively etched (b) in TMAH 5% and (c) without the oxide-nitride HM [127].

Figure 19

(a) Pictorial description of the Si_0.5Ge_0.5/Ge NW stacks used for the selective etch test and SEM images of Si_0.5Ge_0.5-Ge NWs after selective etch for 10 seconds in TMAH with a concentration of (b) 15% and (c) 25% for 45 and 55 nm wide fins [127].

Figure 20

Integration of Co selective growth [148].

Figure 21

Damascence line resistance vs. the total conductor area of Ru, Co, and Cu NWs [142].

Figure 22

22-nm half-pitch Co lines/ALD TiN liner compared to Cu [139].

Figure 23

Performance of Co and Cu EM with 1-nm ALD TiN liner [139].

Figure 24

EM lifetime distributions for the Co and Cu alloy [157].

Figure 25

(a) Schematic image of the band alignment of the Ge and Si channel gate stacks during NBTI stress. The Ge/Si valence band offset (Si-passivated Ge FETs) causes the inversion layer to energetically move away from the oxide traps [161] and (b) defect energy profiles after filling at low and high Vgch vs. Vgdisch-ΔVth. The insets illustrate the charging mechanisms for two different types of electron traps [162].

Figure 26

(a) NBTI V_T shift vs. Eox after 1000 s for all effective La doses in PMOS. La addition causes enhancement of NBTI V_T degradation and (b) PBTI V_T shift vs. Eox after 1000 s for all La doses for NMOS. La addition causes reduction of PBTI V_T degradation [168].

Figure 27

(a) CMOS flow and schematics for NFET with SIGMA/W stack and PFET with TiN/W stack and (b) PBTI improvement mechanism for the SIGMA stack [174].

Figure 28

Peak temperature rise in nano-sheet FETs with increased width of nano-sheets (Wsh) [179]. H_sh stands for height or thickness of nano-sheets.

Figure 29

Illustration of the complex RTN induced by a single trap with an additional one or two metastable states, named as MS-cRTN [181].

Figure 30

TEM micrographs of completed devices. (a) Devices across one gate pattern. (b) 9.5 nm-wide channel obtained from 2 cycles of WHALE* where 1 nm conformal interfacial layer was grown by ALD before HfO₂ deposition. (c) 7 nm-wide channel obtained from 5 cycles of WHALE* with the same gate stack as shown in (b) are used, and (d) along the trench showing L_g of 36 nm [186]. * WHALE stands for Wet HCl-based Atomic Layer Etch.

Figure 31

Cross-section images of the self-aligned InGaAs-OI FinFET architecture where (a) the scaled HKMG deposited on a 15-nm-wide fin using a highly conformal and uniform PEALD* process [192], and (b) shows CS STEM images across the gate showing the InGaAs FinFET with L_g = 13 nm [194]. * plasma-enhanced atomic layer deposition.

Figure 32

Drawing of different 2D materials [205].

Figure 33

(a) Schematic of fabrication, a WSe₂/MoS₂ hetero-structure dual-channel FET. (b) Optical picture of a processed transistor. The dashed line shows the bottom MoS₂ layer, (c) schematic of electron and hole transport in one channel of dual-channel FET, and (d) band diagram WSe₂-Pt metal (top) and MoS₂-Ti. The symbol ϕ_b in the picture stands for the barrier for hole and electrons [206].

Figure 34

(a) and (b) Electronic band structures of 2H and 1T’ MoS₂ and their atomic structures. The 2H band structure shows a bandgap of approximately 1.8 eV, while the conduction and valance bands of 1T’ MoS₂ overlap. Therefore, 1T’ MoS₂ has metallic gapless characteristics. (c) Transfer characteristics of three MoS₂ FETs with different thicknesses of MoS₂ before and after phase transition treatment. The intrinsic 2H MoS₂ FETs show strong semiconducting behavior with large gate modulation, while the phase transition shows constant current with almost no gate modulation featuring, and (d) PL (photoluminescence)spectra of the monolayer 2H and 1T’ MoS₂. The 2H phase shows a strong PL peak at 1.85 eV generated by its bandgap, while the PL of the 1T’ phase is completely quenched due to its gapless metallic characteristics [207].

Figure 35

(a) Schematic of advanced 2D stacks and (b) characteristic curves of the transistor.

Figure 36

3D APT volume based on the standard reconstruction algorithm after density correction of GAA (a) and tri-gate (b) silicon nanowire transistor [229].

Figure 37

RSM and fits to the scattering profile of samples [250].

Figure 38

Geometry of GISAXS experiments [252].