GFET Asymmetric Transfer Response Analysis through Access Region Resistances

Abstract

Graphene-based devices are planned to augment the functionality of Si and III-V based technology in radio-frequency (RF) electronics. The expectations in designing graphene field-effect transistors (GFETs) with enhanced RF performance have attracted significant experimental efforts, mainly concentrated on achieving high mobility samples. However, little attention has been paid, so far, to the role of the access regions in these devices. Here, we analyse in detail, via numerical simulations, how the GFET transfer response is severely impacted by these regions, showing that they play a significant role in the asymmetric saturated behaviour commonly observed in GFETs. We also investigate how the modulation of the access region conductivity (i.e., by the influence of a back gate) and the presence of imperfections in the graphene layer (e.g., charge puddles) affects the transfer response. The analysis is extended to assess the application of GFETs for RF applications, by evaluating their cut-off frequency.

Keywords: GFET; RF; access region.

Figure 1

Schematic of the simulated GFET and the characteristic resistances of the device. The dashed and dotted rectangles indicate the regions used for the different simulations. While the dotted rectangle only encompasses the channel region, the dashed one includes the access regions.

Figure 2

Comparison between the simulation results and the experimental data extracted from [29] (a) and [30] (b).

Figure 3

$I_{\mathrm{DS}}-V_{\mathrm{FG}}$ curves of the device without (a) and with (b) access regions.

Figure 4

Resistance of the three device regions (channel, source and drain access regions) compared with the total resistance as a function of the gate potential, for two $V_{\mathrm{DS}}$ values: −0.1 V (solid) and −0.2 V (dashed).

Figure 5

Transfer response (a,b) and structure resistances (c,d) as a function of the gate bias. These results are obtained reducing the length of either the source (a,c, solid lines) or drain access region (b,d, dashed lines) down to 17.5 nm, and increasing the length of either the source (a,c, solid lines) or the drain access region (b,d, dashed lines) up to 70 nm.

Figure 6

$I_{\mathrm{DS}}-V_{\mathrm{FG}}$ characteristics of the complete structure when three different back gate potentials are used (−1 V (a), 0 V (b) and 1 V (c)). Solid lines correspond to the device without puddles and dashed lines to the device with $N_{\mathrm{p}}={10}^{12}$ cm${}^{-2}$.

Figure 7

Total (a), channel (b), source (c) and drain (d) resistances for different back gate biases and $V_{\mathrm{DS}}=-$0.1 V. Solid lines (referred to the left axis) correspond to the no puddles scenario while dashed lines (referred to the right axis) depict the values obtained when a puddle concentration of $N_{\mathrm{p}}={10}^{12}$ cm${}^{-2}$ is considered.

Figure 8

$f_{\mathrm{T}}$ of the back-gated device with access regions under two scenarios: no puddles (solid lines) and $N_{\mathrm{p}}={10}^{12}$ cm${}^{-2}$ (dash-dotted lines). The values obtained for the intrinsic device are depicted by the purple dashed line. The arrows labelled by marks on the right side axis indicate the values of $f_{\mathrm{T}}$ extracted from [35] (circle) and [36] (square and triangle). The yellow line indicates the physical limit for graphene $v_{\mathrm{F}}/2\pi L$, determined by the transit time $L/v_{\mathrm{F}}$, with the Fermi velocity $v_{\mathrm{F}}\approx {10}^8$ cm/s and $L=$ 100 nm (squares).