Reduction of charge impurities in a silicon metal-oxide-semiconductor quantum dot qubit device patterned with nano-imprint lithography

Abstract

The silicon metal-oxide-semiconductor quantum dot architecture is a leading approach for the physical implementation of semiconductor quantum computing. One major challenge for scalable quantum dots is the presence of charge impurities. Electron-beam lithography (EBL), almost universally used to fabricate quantum dot devices, is known to create such defects at the Si/SiO₂ interface. To eliminate the need for EBL, we have transferred the metal gate pattern of a quantum dot onto the silicon substrate using nano-imprint lithography. Critical features with 50 nm scale and separation can be dependably reproduced. By characterizing the bias-dependent charge transport through a quantum point contact barrier, the prevalence of impurities is found to be largely diminished in nano-imprinted devices when compared to similar electron-beam-written counterparts. High-quality charge transport and charge sensing of several quantum dots are obtained. Additionally, gate noise is measured with an average of 1.5 μeV Hz^-1/2 equivalent to previous measurements made on devices fabricated with EBL, which suggests that the leading source of impurities produced by EBL are deep, fixed charges. This work offers a path toward reliable quantum dot operation in MOS by improving fabrication techniques to reduce charge impurities.