An Impulse Radio PWM-Based Wireless Data Acquisition Sensor Interface

Abstract

A sensor interface circuit based on impulse radio pulse width modulation (IR-PWM) is presented for low power and high throughput wireless data acquisition systems (wDAQ) with extreme size and power constraints. Two triple-slope analog-to-time converters (ATC) convert two analog signals, each up to 5 MHz in bandwidth, into PWM signals, and an impulse radio (IR) transmitted (Tx) with an all-digital power amplifier (PA) combines them while preserving the timing information by transmitting impulses at the PWM rising and falling edges. On the receiver (Rx) side, an RF-LNA followed by an envelope detector recovers the incoming impulses, and a T-flipflop reverts the impulse sequence back to PWM to be digitized by a time-to-digital converter (TDC). Detailed analysis and design guideline on ATC was introduced, and a proof-of-concept prototype was fabricated for a capacitive micromachined ultrasound transducer (CMUT) imaging system in a 0.18-μm HV CMOS process, occupying 0.18 mm² active area and consuming 3.94 mW from a 1.8 V supply. The proposed TDC in this prototype yielded 7-bit resolution, while the entire wDAQ achieved 5.8 effective number of bits (ENOB) at 2 × 10 MS/s.

Keywords: Pulse width modulation; impulse radio; wideband communication; wireless data acquisition.

Fig. 1.

Operational diagram of pulse width modulated impulse radio (IR-PWM) wireless data acquisition (wDAQ). The information in the analog input signal (V) is converted into a pulse with the width of α × I. In FSK-PWM, a frequency-modulated sinusoidal wave is generated at two frequencies that represent ‘1’ and ‘0’ of the PWM pulse. In IR-PWM, sharp impulses are transmitted at every rising and falling edge of the PWM signal, as shown in the bottom trace.

Fig. 2.

(a) Schematic and (b) timing diagrams of the dual-slope charge sampling AFE [18].

Fig. 3.

Schematic diagram of the proposed IR-PWM wDAQ as part of a guidewire IVUS imaging system [4]. (a) SoC Tx and (b) COTS Rx.

Fig. 4.

Timing diagram of the proposed triple-slope charge sampling IR-PWM.

Fig. 5.

(a) Schematic diagrams of the OTA, (b) comparator with source-coupled differential pair, and (c) impulse generator.

Fig. 6.

Integral nonlinearity (INL) of the OTA in simulations.

Fig. 7.

Ideal UWB impulse and sum of two impulses with different delays.

Fig. 8.

(a) Theoretical maximum error rate and resolution obtained from ideal UWB impulse, and (b) accuracy requirement of the TDC on the Rx side, and (c) spectrum of IR-PWM.

Fig. 9.

Die photo of the IR-PWM transmitter in 0.18-μm HV CMOS process.

Fig. 10.

Measurement results for 7-bit (a) INL and (b) DNL.

Fig. 11.

(a) Measurement setup of the IR-PWM transceiver and (b) die photo of the Rx ASIC.

Fig. 12.

Measured signals from Tx PWM, Tx output, COTS Rx output, and recovered Rx ASIC output PWM with 30 ns latency.

Fig. 13.

Spectrum of decoded Tx output, COTS Rx output, and Rx ASIC output.

Fig. 14.

Histogram of the measured clock jitter.