Junctionless Dual In-Plane-Gate Thin-Film Transistors with AND Logic Function on Paper Substrates

Abstract

Dual-gate thin-film transistors (DGTFTs) have attracted increasing attention in the past few years because of threshold voltage modulation and device logic functionality. Here, solution-processed chitosan-based proton conductors are used as the gate dielectric. The threshold voltage shift depends on the ratio of the capacitances of the two gate dielectrics. The second interesting application of DGTFTs is logic functionality. This device demonstrates AND logic function controlled by applying either 0 or -1 V to each of the gate electrodes. When both gates were simultaneously applied to be 0 V, the current flows (ON). Otherwise, the current is blocked (OFF). In order to provide a comprehensive overview of these paper devices, the planarization of paper surface and switching stability of such DGTFTs are all discussed.

Figure 1

(a) Schematic picture of junctionless dual-gate paper TFTs. (b) Equivalent circuit of such junctionless DGTFTs. (c) Specific gate capacitance of junctionless dual-gate paper TFTs. (d) Leakage current of such TFTs.

Figure 2

(a) I_DS–V_GS curves of junctionless DGTFTs on paper substrates with various channel thicknesses (T_ITO = 5, 20, 40, and 60 nm) at V_DS = 1.5 V. (b) I_DS–V_DS curve for a fresh device with T_ITO = 20 nm.

Figure 3

(a) Transfer characteristics of such junctionless DGTFTs on paper substrates with V_G3 ranging from 2 to −2 V. (b) (I_DS)^1/2 vs V_G3 curves.

Figure 4

(a) V_th and I_on/off ratio of such DGTFTs on paper substrates at different V_G3. (b) μ and S of such DGTFTs on paper substrates at different V_G3.

Figure 5

(a) Low-frequency pulse respond characteristic of the device with V_G2 = −0.5 to 1.5 V, V_G3 = 0 V, and V_DS = 1.5 V. (b) AND logic function with a large I_on/off.