Memristor-Based Edge Detection for Spike Encoded Pixels

Abstract

Memristors have many uses in machine learning and neuromorphic hardware. From memory elements in dot product engines to replicating both synapse and neuron wall behaviors, the memristor has proved a versatile component. Here we demonstrate an analog mode of operation observed in our silicon oxide memristors and apply this to the problem of edge detection. We demonstrate how a potential divider exploiting this analog behavior can prove a scalable solution to edge detection. We confirm its behavior experimentally and simulate its performance on a standard testbench. We show good performance comparable to existing memristor based work with a benchmark score of 0.465 on the BSDS500 dataset, while simultaneously maintaining a lower component count.

Keywords: computer vision; edge detection; memristor; neuromorphic computing; spiking neural networks.

Figure 1

(A) Our devices use an active layer of 35 nm sputtered amorphous silicon oxide. The bottom contact is a 280 nm layer of molybdenum and the top contact is a 115 nm layer of gold with a 3 nm wetting layer of titanium. (B) Examples of the current transients which occur when constant negative voltages are applied to the top electrode with respect to the bottom electrode. Transients consist of two parts. There is an initial increase in conductance and a subsequent decrease. In this work we operate only within the first region, the increase in conductance. Inset is a plot of the absolute voltage across the device during the initial stressing stage. A constant current of −10μA is driven through the device. The applied voltage decreases over time, indicating the reduction in device resistance that occurs as a result. (C) Negative and positive voltages have an opposite effect on the device's conductance. When a train of negative voltage spikes were applied to the device in a potential divider setup with a fixed 1MΩ resistor, the voltage of spikes at the output increases over time (black trace), corresponding to an increase in conductance of the memristor. In contrast, when a train of positive spikes are interleaved in anti-phase with the negative spikes (red trace), the output voltage increases to a lesser extent. This demonstrates the competing effects positive voltages have on the memristor. The positive spikes are reversing the changes in conductance cause by the negative spikes. (D) Setup to demonstrate the competing effects of negative and positive polarities. Gaussian pulses with a full width at half maximum (FWHM) of 1.3 ms are generated by a signal generator. These are applied to the top contact of the memristor which is in a potential divider with a fixed 1MΩ resistor. The output voltage, V_pot, is measured at the output of the potential divider. (E) Our circuit that determines the difference in frequency of two input spike trains. Both inputs generate pulse trains with a negative amplitude and a frequency proportional to their input value. Each input is connected to a single memristor. Both memristors then join at a common node. The output of the circuit, V_out, is taken at this common node. The amplitude of output spikes indicate the difference between the two input frequencies. Larger differences in frequency result in larger amplitudes at the output.

Figure 2

Experimental data demonstrating the circuit's ability to detect differences in frequency between two input spike trains. Two scenarios are presented: the first with no difference in input frequency and the second with a difference of 50 Hz. Spikes are Gaussian shaped with a full width at half maximum (FWHM) of 1.3 ms. Each Gaussian pulse has been cropped to a width 2 ms. (A,C) These show the input and output signals, respectively, for the case of no difference in input frequency. Both input 1 (red trace) and input 2 (black trace) are set to 50 Hz. In the plot beneath we see the amplitude of spikes at the output remain approximately constant for both inputs. For clarity we have included an envelope tracking the output spikes caused by input 1 (dotted red trace) and input 2 (dotted black trace). (B,D) Shows the input and output signals, respectively, for the case with a 50 Hz difference in input frequency between the two inputs. Input 1 is set to 100 Hz while input 2 remains at 50 Hz. For clarity, we have again overlaid two envelopes tracking the output spikes caused by input 1 and input 2. This time, we observe at the output that spikes caused by input 1 increase in amplitude over time, whereas those from input 2 remain constant.

Figure 3

(A) An illustration of how edge detection would be implemented. The circuit is placed between two neighboring pixels. Large differences in pixel values will produce output spikes with larger amplitudes. (B) The look-up map describing our circuit's behavior. The average amplitude of output spikes above a threshold is plotted along the z axis. We use this look-up table during simulations. It approximates the circuit's output for any given pair of input frequencies. The sampling points from which this map was interpolated from are illustrated with red circles. (C) Benchmarking results on the BSDS500 dataset. The distribution of F-Measures, defined in Arbeláez et al. (2011) are plotted for memristive techniques (green) and standard operators (blue). The results are obtained from the set of 200 test images provided by BSDS500. (D) Comparison of F-Measure scores for a set of operators using both the original test images and images produced by our own circuit as their input. An improvement in performance is observed over the Prewitt, Sobel, and log operators.

Figure 4

(A) A sample of the original input images presented to the circuit. Source: Arbeláez et al. (2011). In simulation, there exists an edge detection circuit between each neighboring pixel. Pixels are mapped from their 0–255 value to a frequency range between 50–100 Hz. (B) The corresponding output images of the simulation. Each pixel represents the output of an edge detection circuit placed between two neighboring pixels. The average amplitude of output spikes above a threshold is mapped from the voltage to a pixel value from 0 to 255 and is plotted in this image. Brighter pixels indicate edges. We have combined the simulations of edge detection in both the vertical and horizontal plane.

Figure 5

(A,B) The circuit response plotted in two different perspectives for clarity. The response for two circuits are presented in both figures, a potential divider of two high resistance devices (red markers) and a potential divider of two low resistance devices (green markers). Markers represent the inputs sampled for the circuit. (C) The circuit response when devices have asymmetric resistances. The red markers indicate the points sampled from the circuit. (D) The effect of device variance on circuit performance. The circuit's benchmark score (F-Measure) is plotted for a range of simulations where variations in device resistances were introduced. Device variations were distributed randomly and with a Gaussian distribution. The standard deviation of device resistances were increased with the effect of a reduction in performance. For reference the score of a system randomly categorizing pixels as edges is also plotted.

Figure 6

The effect of image resolution on circuit performance. The benchmarking score (F-Measure) is plotted against the scale factor of the image resolution. An improvement in performance is observed for lower resolution images. For example, the highest score occurred when the images were at a 1/3 of their original resolution. It was not possible to investigate the effect of increasing image resolution as there were no high resolution images available for the dataset.