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. 2020 Mar 2;20(5):1362.
doi: 10.3390/s20051362.

A Model-Based Design Floating-Point Accumulator. Case of Study: FPGA Implementation of a Support Vector Machine Kernel Function

Marco Bassoli  1 , Valentina Bianchi  1 , Ilaria De Munari  1
Affiliations

A Model-Based Design Floating-Point Accumulator. Case of Study: FPGA Implementation of a Support Vector Machine Kernel Function

Marco Bassoli et al. Sensors (Basel). .

Abstract

Recent research in wearable sensors have led to the development of an advanced platform capable of embedding complex algorithms such as machine learning algorithms, which are known to usually be resource-demanding. To address the need for high computational power, one solution is to design custom hardware platforms dedicated to the specific application by exploiting, for example, Field Programmable Gate Array (FPGA). Recently, model-based techniques and automatic code generation have been introduced in FPGA design. In this paper, a new model-based floating-point accumulation circuit is presented. The architecture is based on the state-of-the-art delayed buffering algorithm. This circuit was conceived to be exploited in order to compute the kernel function of a support vector machine. The implementation of the proposed model was carried out in Simulink, and simulation results showed that it had better performance in terms of speed and occupied area when compared to other solutions. To better evaluate its figure, a practical case of a polynomial kernel function was considered. Simulink and VHDL post-implementation timing simulations and measurements on FPGA confirmed the good results of the stand-alone accumulator.

Keywords: FPGA; HDL code generation; embedded devices; model-based design; wearable sensors.

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Conflict of interest statement

The authors declare no conflict of interest.

Figures

Figure 1
Figure 1
Simulink multi-set delayed buffering (DB) accumulator implementation.
Figure 2
Figure 2
Architecture of the Input Buffer (IBUF) block.
Figure 3
Figure 3
Simulink cubic kernel implementation.
Figure 4
Figure 4
Input and output signals of the multi-set DB accumulator in Simulink simulation: (a) Input vector values, (b) Data_last signal, (c) Data_valid signal, (d) Accumulator output value, and (e) Result_ready signal.
Figure 5
Figure 5
Kernel performance in Simulink simulations: (a) Kernel with proposed accumulator, (b) Kernel with Simulink IP accumulator.
Figure 6
Figure 6
Xilinx Vivado post-implementation results of the kernel with (a) Kernel with proposed accumulator, (b) Kernel with Simulink IP accumulator.
Figure 7
Figure 7
Experimental setup for the hardware measurement.
Figure 8
Figure 8
Measurement of the processing time of the kernel with the proposed accumulator implemented on the FPGA.
Figure 9
Figure 9
Measurement of the processing time of the kernel with Simulink IP implemented on the FPGA.
See this image and copyright information in PMC

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