Supervised Learning in All FeFET-Based Spiking Neural Network: Opportunities and Challenges

Abstract

The two possible pathways toward artificial intelligence (AI)-(i) neuroscience-oriented neuromorphic computing [like spiking neural network (SNN)] and (ii) computer science driven machine learning (like deep learning) differ widely in their fundamental formalism and coding schemes (Pei et al., 2019). Deviating from traditional deep learning approach of relying on neuronal models with static nonlinearities, SNNs attempt to capture brain-like features like computation using spikes. This holds the promise of improving the energy efficiency of the computing platforms. In order to achieve a much higher areal and energy efficiency compared to today's hardware implementation of SNN, we need to go beyond the traditional route of relying on CMOS-based digital or mixed-signal neuronal circuits and segregation of computation and memory under the von Neumann architecture. Recently, ferroelectric field-effect transistors (FeFETs) are being explored as a promising alternative for building neuromorphic hardware by utilizing their non-volatile nature and rich polarization switching dynamics. In this work, we propose an all FeFET-based SNN hardware that allows low-power spike-based information processing and co-localized memory and computing (a.k.a. in-memory computing). We experimentally demonstrate the essential neuronal and synaptic dynamics in a 28 nm high-K metal gate FeFET technology. Furthermore, drawing inspiration from the traditional machine learning approach of optimizing a cost function to adjust the synaptic weights, we implement a surrogate gradient (SG) learning algorithm on our SNN platform that allows us to perform supervised learning on MNIST dataset. As such, we provide a pathway toward building energy-efficient neuromorphic hardware that can support traditional machine learning algorithms. Finally, we undertake synergistic device-algorithm co-design by accounting for the impacts of device-level variation (stochasticity) and limited bit precision of on-chip synaptic weights (available analog states) on the classification accuracy.

Keywords: analog synapse; ferroelectric FET; neuromorphic computing; spiking neural network; spiking neuron; supervised learning; surrogate gradient learning.

FIGURE 1

(A) Schematic of a spiking neural network consisting of an array of plastic synapses and a spiking neuron. A key element of the spiking neuron is the neuronal membrane, which is represented by the intrinsic state variable, i.e., the ferroelectric polarization. (B) Schematic of a metal-ferroelectric-metal (MFM) capacitor consisting of 10 nm ferroelectric Hf_xZr_1–xO₂ thin film sandwiched between two Tungsten (W) metal electrodes that is used to investigating the voltage-dependent polarization switching dynamics. (C) Experimentally measured polarization vs electric field (P-E) loop exhibiting saturation as well as minor loops owing to the presence of multiple domains in such ferroelectric thin film. By applying short sub-coercive voltage pulses (D), we can measure the transient polarization switching highlighting the temporal integration of applied voltage pulses and relaxation during the absence of input pulse (E). This inherent polarization dynamics closely resembles the neuronal membrane dynamics of the LIF neuron.

FIGURE 2

(A) Schematic and TEM of a high-K metal gate FeFET with a poly-Si/TiN/Si:HfO2/SiON/p-Si gate stack fabricated at 28 nm technology node. (B) On application of successive sub-coercive voltage pulses to the gate of FeFET, the threshold voltage V_T gets modulated abruptly from a high-VT to low-VT state. (C) Corresponding conductance modulation as a function of number of applied pulses, measured over multiple cycles. (D) The integrate-and-fire dynamics of the FeFET neuron. After reaching a conductance threshold, the FeFET is reset to the initial polarization state using a negative gate voltage, which results in a sequence of firing events. (E,F) Distribution of inter-spike interval for a range of voltage amplitudes and the corresponding stochastic firing rate of the FeFET neuron. Similar impact of varying the input pulse width on the inter-spike interval and firing rate is seen in (G,H).

FIGURE 3

(A) Circuit implementation of a FeFET-based spiking neuron. The LIF neuron is implemented using one FeFET and three transistors (M1–M3). Biologically inspired homeostatic plasticity is implemented using additional transistors (M4–M6). (B) SPICE circuit simulation of the FeFET-based LIF spiking neuron with spike frequency adaptation. (C) Decrease in the instantaneous firing rate of the neuron with each output spike, exhibiting spike frequency adaptation.

FIGURE 4

(A) FeFET-based pseudo-crossbar array enabling analog vector–matrix multiplication and row-wise parallel weight update of the synaptic weight with column-wise summation. (B) Measured Id–Vg characteristics of a 500 nm × 500 nm FeFET upon applying amplitude modulated voltage pulses. Applying progressively increasing gate pulses V_P causes the FeFET to transition from the initial high-V_T state to lower V_T states. (C) Corresponding channel conductance of the FeFET upon applying progressively increasing gate pulses V_P, measured over multiple cycles. (D) Measured eight non-overlapping G_DS states obtained over multiple cycles using both potentiation and depression pulses that allows the representation of a 3-bit analog weight cell. (E) Cumulative distribution of the G_DS states corresponding to potentiation pulse scheme obtained over multiple cycles.

FIGURE 5

(A) We performed supervised learning on MNIST dataset using a three-layer SNN. The input layer consists of 784 neurons while the output layer has 10 neurons to classify the digits. We additionally use a Bayesian hyperparameter optimization approach (Bergstra et al., 2013) to determine the number of neurons in the hidden layer. (B) Training accuracy as a function of the number of training epochs for different synaptic weight bit precision (analog states). (C) Impact of stochastic noise (incorporated as uniform threshold noise) on the test accuracy for different weight bit precision. (D) Comparison of test accuracy for different weight bit precision with and without noise.