State of the Art and Future Perspectives in Advanced CMOS Technology

Abstract

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

Keywords: CMOS; epitaxy; nano-scale transistors; process integration.

Figure 1

Schematics of vertical gate-all-around field effect transistors (GAAFETs): (a) Vertical nanosheet GAAFET and (b) vertical nanowire GAAFET. Vertical nanowires—Lg and spacer dimension are decoupled from the gate pitch. Density is determined by distance between the wires. Many process challenges. [37].

Figure 2

TEM cross-section of a Si channel vertical GAAFET (vGAAFET) with channel last or growth from bottom to top after the formation of bottom bottom borosilicate glass (BSG), gate layer, and top BSG layers [38].

Figure 3

Carrier mobility in inversion layers and quantum wells in Si, Ge, and III-V compounds. Red symbols represent electron mobility and blue ones are marked for hole mobility. The electron mobility in the compounds shown in the plots are much higher than that in Si and Ge [50].

Figure 4

InAs vGAAFET formed by vapor-liquid-solid (VLS) bottom-up method: (a) Nanowires after thinning of channel regions and (b) final device structures with high-k metal gates [41].

Figure 5

For an InAs vGAAFET consisting of 280 nanowires in parallel with a diameter of 28 nm and gate length of 190 nm: (a) Transfer characteristics and (b) output characteristics [41].

Figure 6

In_0.53Ga_0.47As nanosheet FET made by a top-down method: (a) TEM cross-section and (b) the transfer characteristics [45].

Figure 7

Process flow for vertical sandwich GAAFET (VSAFETs): (a) SEM after Si/SiGe/Si, (b) SEM tilt image of the 3D nanostructure after Reactive ion etching (c) SEM after quasi-atomic layer etching (QALE), and (d) TEM after high-k and metal gates (HKMG) deposition [46].

Figure 8

(a) Secondary ion mass spectrometry (SIMS) profiles of B and Ge in a p-Si/i-SiGe/p-Si sandwich film [31]. An abrupt B profile was achieved by in-situ doped epitaxial growth. (b) TEM cross-sections of an NS pVSAFET with an Si cap and an HKMG stack with interface layer (IL) = 1.1 nm [46].

Figure 9

A design of buried interconnects for vGAAFETs [59].

Figure 10

(a–d) Tunneling field-effect transistor (TFET) characterization: (a) SEM of a nanowire (NW) with a diameter of 10 nm when the layers are S1 = InAs, S2 = InGaAsSb, and S3 = GaSb, and (b) schematic of TFET structure in (a,c) transfer characteristics of a TFET with diameter of 20 nm, and (d) output characteristics of the same transistor in (c) [63].

Figure 11

Illustration of the hierarchy of technology computer-aided design (TCAD) device models [64].

Figure 12

Illustration of the density functional theory (DFT)-nonequilibrium Green’s function (NEGF) self-consistent simulation flow [67].

Figure 13

Illustration of the tight-binding (TB)-NEGF self-consistent simulation flow [70].

Figure 14

Ilustration of the advanced drift-diffusion (DD) calibration and applications [73].

Figure 15

Resolution, dose sensitivity, and their relationship to low line edge roughness (LER).

Figure 16

An image of 24 nm pitch lines which are successfully implemented through extreme ultraviolet (EUV) single-patterning process [88].

Figure 17

Ge contents in source and drain (S/D) regions in different technology nodes [92].

Figure 18

(a) The image of the processed chips on an 200 mm wafer where three groups were distinguished according to the transistor performance and (b) illustrates the pattern of one 112 manufactured chips where the different exposed Si areas are shown in different colors [94].

Figure 19

HRTEM cross-section micrographs of the Si-fins with different prebaking temperatures as follows: (a) at 825 °C and (b) 800 °C [104].

Figure 20

Cross-section TEM image of strained Ge-cap/ SRB Si_0.3Ge_0.7SEG grown inside oxide trenches of FinFET [110].

Figure 21

A vertical gate-all-around nanowire structure [111].

Figure 22

A manufacturing process of horizontal GAA-FETs (hGAA-FETs).

Figure 23

Schematic of VLS growing nanowires [117].

Figure 24

TEM images of post-etching of Si/SiGe multilayer fins in two directions (longitudinal and transverse cross-section). Two fin-patterning options have been designed: (a) Isolated and (b) dense FETs, which were carried out by sidewall pattern transfer technology [112].

Figure 25

Interfacial layer and high-k dielectric thickness from 45 nm to 5 nm node.

Figure 26

Work function metal thicknesses from 45 nm to 5 nm node.

Figure 27

Cross-sectional SEM pictures of W films grown in different conditions: (a) On blank wafers and (b) trenches filling capacity [166].

Figure 28

XRD patterns of ALD W grown by SiH₄ and B₂H₆ precursors and the estimated stress [166].

Figure 29

A spectrum shows the improvement of tensile stress using ultraviolet thermal process (UVTP) method [172].

Figure 30

Light transparent window of the core materials for different waveguide and the white areas represent optical transparency meanwhile the blue areas signify high energy loss [178].

Figure 31

NMOSFET electron mobility vs. contact etch stop layer (CESL) technology, (a) in 9 nm n-FET NW. A better mobility is observed under tensile CESL [187] and (b) Electron mobility vs. L for different CESL in nanowires. Inset: extracted access resistance [188].

Figure 32

Process flow and critical etching steps for manufacturing lateral nanowire GAA device: (a) Source/drain Fin recess for opening active area, (b) cavity etching for defining the growth position and size of the inner spacer, (c) inner spacer film deposition, (d) controlled etching of spacer film and formation of inner spacer, (e) source/drain epitaxial growth, (f) dielectric deposition and planarization, (g) dummy gate removal and nanowires formation, (h) filling and planarization of high-K metal gates, (i) interlayer dielectric deposition, and (j) metal contact plug and current direction when device is on on-state [195].

Figure 33

Schematic of vertical nanowire GAA transistor: (a) Structural design for a single device, and (b) test structure with two devices connected in parallel via a local interconnect bridge [46].

Figure 34

The SEM images of cross section comparing the profile between wet etching and inductively coupled plasma (ICP) dry etching: (a) Wet etching SiGe with 6% HF/30% H₂O_2/99.8% CH₃COOH = 1:2:4 etching 8 min, and (b) ICP dry etching SiGe with CF₄ /O₂ /He = 4:1:5 [207].

Figure 35

High-reosultion reciprocal lattice maps (HRRLMs) in the vicinity of the asymmetric (113) Bragg reflection acquired on SiGe/SiMLS: (a) Unprocessed structure; (b) after vertical anisotropic etch and 100:1 DHF wet clean, and (c) lateral isotropic SiGe selectivite by using ICP dry etching [207].

Figure 36

TEM and EDX mapping: (a) TEM picture of all structures; (b) HRTEM and EDS mapping of near isotropic etching region [113].

Figure 37

TEM and EDS micrographs: (a) LPCVDSilicon nitride inner spacer deposition; (b) inner spacer after etching under optimal conditions [195].

Figure 38

Contact angle test of C1 and C8 [243].

Figure 39

ATR-IR spectrum measured from silicon oxide powder treated with C1 or C8 shows that C1 has better result because of higher hydrocarbon groups around 750 to 900 cm⁻¹, while lower hydroxyl group at 960 cm⁻¹ [243].

Figure 40

Top-view SEM image of samples treated with C1 and C8 after drying [243].

Figure 41

Through-Co self-forming barrier (tCoSFB) structure and process flow: (a) Ultra-thin Ta(N)/CVD-Co/ high-Mn% PVD-Cu(Mn) seed stack layer deposition; (b) Cu electroplating and anneal; (c) Cu CMP; (d) PECVD SiCN(H) dielectric cap and TaMnxOy SFB formation [277].

Figure 42

Threshold voltage shift (ΔV_T) kinetics at different gate V_G-STR and T under constant V_G stress for ALD W using B₂H₆ and SiH₄. (a) Under constant V_G stress; (b) under constant E_OX stress. The SiH₄-based devices shows reduced negative bias temperature instability (NBTI) degradation than B₂H₆-based devices under both constant V_G and constant E_OX stress [295].

Figure 43

Simulated read static noise margin (SNM) vs. write noise margin (WNM) of the Static Random Acess Memory (SRAM) cell considering HCI degradation and HCI together with BTI degradation after 10⁸s operating time [304].

Figure 44

(a) Measurement schematic illustration for occupancy probability estimation, (b) randomly generated complex waveform for one period, (c) measured window to judge trap state after complex waveforms for each cycle, and (d) comparison between the extracted occupancy probability in experiments and model results [312].

Figure 45

Antiphase boundaries (APDs) occurs when (a) GaAs is grown on an incomplete pre-layer coverage Ge substrate or with (b) odd atoms layer step, and (c) self-annihilating of APDs when GaAs is grown on cut-off substrate.

Figure 46

(a) Reduction of threading dislocation density (TDD) at layer interfaces in a superlattice (SL). Dislocations are bent at the interfaces in SL [321], and (b) a TEM image of a part of a SL structure with GaAs buffer layer grown by LT/HT multi-steps epitaxy [324]. The TEM image shows the TDs are restricted at InGaAs/GaAs interface and do not propagate further in the same direction.

Figure 47

(a) V-groove aspect ratio trapping (ART) process flow, (b) the SEM diagram of the tilted V-groove patterned Si and, (c) the atomic force microscope (AFM) of GaAs on patterned Si, respectively [333].

Figure 48

Structures of complementary metal oxide semiconductor (CMOS), which are composed of III-V nMOSFET and Ge p type Metal-Oxide-Semiconductor Field-Effect Transistor (pMOSFET) [342].

Figure 49

Possible evolution scenario for III–V/Ge devices on Si platform through heterogeneous integration [343].

Figure 50

Critical issues of Ge/III-V integration with Si CMOS platform [344].

Figure 51

The structure of InGaAs high electron mobility transistors (HEMTs) designed for logic applications [345].

Figure 52

Schematic illustration of the III-V semiconductor channel fin-shaped field effect transistor with a charged dislocation located at center of channel and vertical to the top gate surface [347].

Figure 53

Process flow of InGaAs devices fabricated on 200 mm Si wafers and schematic of transistor structure [348].

Figure 54

Band structure of n⁺ InAlAs/InGaAs heterojunction.

Figure 55

A typical structure of InP HEMT [358].

Figure 56

Layer structure of the first HEMT device based on InP.

Figure 57

Left to right: Graphene lattice, electronic bandstructure, linear dispersion at low energies, pseudospin components, and density of states (DOS) dependence on energy [384].

Figure 58

Drawing of different 2D materials [385].

Figure 59

Schematic illustration of the electrochemical Li intercalation-assisted liquid exfoliation method for preparation of single- or few-layer transition metal dichalcogenide (TMD) nanosheets [394].

Figure 60

Schematic of the growth of chemical vapor deposition (CVD) system for MoS₂ and WS₂ [396].

Figure 61

SEM images of (a) the cross-section and (b) the top view of MoS₂NF/rGO. Highly magnified SEM images of the top view of (c) MoS₂NF/rGO and (d) MoS₂AG/rGO [399].

Figure 62

High-resolution scanning tunneling microscope (STM) graphene nanoribbons (GNR) characterization and FET structure: (a) STM image of synthesized 9AGNR on Au with a scale bar of 10 nm (V_s = 1 V, I_t = 0.3 nA). Inset: High-resolution STM image of 9AGNR on Au (V_s = 1 V, I_t = 0.5 nA) with a scale bar of 1 nm, (b) high-resolution STM image of 13AGNR on Au with a scale bar of 2 nm (V_s = −0.7 V, I_t = 7 nA), (c) schematic of the short channel GNRFET with a 9AGNR channel and Pd source-drain electrodes, and (d) scanning electron micrograph of the fabricated Pd source-drain electrodes with a scale bar of 100 nm [400].

Figure 63

Fabrication and structure of few-layer MoS₂ photodetector. (a) Schematic structure of triple-layer MoS₂; (b) Schematic structure of P(VDF-TrFE) ferroelectric polymer; (c) Optical image of the whole device; (d) 3D schematic view of the triple-layer MoS₂ photodetector with monochromatic light beam [406].

Figure 64

(a) TEM and (b) SEM images of MXene flakes after delamination and before film manufacturing. (c) A schematic illustration of MXene-based functional films with adjustable properties [409].

Figure 65

(a) Typical back-gate graphene-based field-effect transistor (GFET) on Si/SiO₂ substrate used as gas sensor, and (b) typical solution-gate GFET on flexible polyethylene terephthalate (PET) substrate used as chemical and biological sensor in aqueous solution [412].

Figure 66

Schematic drawing of the multi-beam SEM.

Figure 67

The shape of 3D AFM.

Figure 68

Conventional atom probe tomography.

Figure 69

HRRLMs of (113) reflection obtained from fins with width of 20 nm in (a) longitudinal and (b) transverse direction [441].

Figure 70

Geometry of grazing incidence small-angle X-ray scattering (GISAXS) experiments [443].

Figure 71

An image of NOVAFit™ applications for advanced nano-scale measurements [447].