Multi-Level Analog Resistive Switching Characteristics in Tri-Layer HfO2/Al2O3/HfO2 Based Memristor on ITO Electrode

Abstract

Atomic layer deposited (ALD) HfO₂/Al₂O₃/HfO₂ tri-layer resistive random access memory (RRAM) structure has been studied with a transparent indium tin oxide (ITO) transparent electrode. Highly stable and reliable multilevel conductance can be controlled by the set current compliance and reset stop voltage in bipolar resistive switching. Improved gradual resistive switching was achieved because of the interdiffusion in the HfO₂/Al₂O₃ interface where tri-valent Al incorporates with HfO₂ and produces HfAlO. The uniformity in bipolar resistive switching with I_on/I_off ratio (>10) and excellent endurance up to >10³ cycles was achieved. Multilevel conductance levels in potentiation/depression were realized with constant amplitude pulse train and increasing pulse amplitude. Thus, tri-layer structure-based RRAM can be a potential candidate for the synaptic device in neuromorphic computing.

Keywords: HfO2/Al2O3/HfO2 tri-layer RRAM; multilevel conductance; synaptic properties; transparent electrode.

Figure 1

Schematic of TaN/HfO₂/Al₂O₃/HfO₂/indium tin oxide (ITO) resistive random access memory (RRAM) device structure with top and a bottom electrode connected to Keithley 4200 SCS semiconductor parameter.

Figure 2

(a,b) Cross-sectional high-resolution transmission electron microscopy (HRTEM) image of TaN/HfO₂/Al₂O₃/HfO₂/ITO tri-layer RRAM structure; (c) EDS elemental mapping; (d) line profiles of Ta, Hf, Al, O, In, and Sn for the cross-section of the device.

Figure 3

(a) Multiple initial forming characteristics under negative applied voltage to the top electrode and first RESET under positive voltage of TaN/HfO₂/Al₂O₃/HfO₂/ITO tri-layer RRAM device; (b) consecutive bipolar resistive switching characteristics of 200 SET/RESET cycles; (c) endurance characteristics of tri-layer RRAM device for 1300 switching cycles at a read voltage of 0.1 V; (d) memory retention of HRS and LRS for 10⁴ s with a read voltage of 0.1 V.

Figure 4

Schematic diagram of resistive switching mechanism of the TaN/HfO₂/Al₂O₃/HfO₂/ITO RRAM during the SET and RESET process.

Figure 5

(a) Multilevel storage of tri-layer RRAM device under varying SET compliance currents from 100 µA to 1 mA; (b) reliability test for data endurance (30 cycles); (c) retention characteristics (10³ s) with the corresponding increasing SET I_cc; (d) bipolar resistive switching with multilevel high resistance state under increasing RESET voltage for tri-layer memristor device; (e) multi-level endurance characteristics under different RESET voltages for 30 cycles each; (f) retention characteristics of LRS and multilevel HRS under different RESET V_stop for 10³ s.

Figure 6

(a) Paired-pulsed facilitation and (b) paired-pulsed depression phenomenon of tri-layer TaN/HfO₂/Al₂O₃/HfO₂/ITO memristor device under pulse spikes of −0.8 V and +1.2 V, respectively, with a time interval of 10 ms; (c) pulse potentiation/depression cycle with constant pulse width of −0.8 V/100 µs and +1.0 V/100 µs, respectively, read at 0.1 V (50 pulses of potentiation and 50 pulses of depression). (d) Repetitive 8 cycles of gradual conductance modulation for consecutive potentiation and depression controlled by increasing step pulse and read at 0.1 V; (e) details of pre-pulse and post-pulse scheme design using time-division multiplexing (TDM) approach to realize spike-timing-dependent plasticity (STDP) properties; (f) STDP characteristics of tri-layer RRAM device shows relative synaptic weight (ΔW) change with respect to spiking timing (Δt).