CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory

Abstract

Ferroelectric memory has been substantially researched for several decades as its potential to obtain higher speed, lower power consumption, and longer endurance compared to conventional flash memory. Despite great deal of effort to develop ferroelectric memory based on perovskite oxides on Si, formation of unwanted interfacial layer substantially compromises the performance of the ferroelectric memory. Furthermore, three-dimensional (3D) integration has been unimaginable because of high processing temperature, non-CMOS compatibility, difficulty in scaling, and complex compositions of perovskite oxides. Here, we demonstrate a unique strategy to tackle critical issues by applying hafnia-based ferroelectrics and oxide semiconductors. Thus, it is possible to avoid the formation of interfacial layer that finally allows unprecedented Si-free 3D integration of ferroelectric memory. This strategy yields memory performance that could be achieved neither by the conventional flash memory nor by the previous perovskite ferroelectric memories. Device simulation confirms that this strategy can realize ultrahigh-density 3D memory integration.

Fig. 1. FeTFT for nonvolatile memory applications.

(A) Schematic illustration of FeTFT that uses HfZrO_x and InZnO_x. (B) Transfer curves of FeTFT with V_DS = 0.1, 0.05, and 0.01 V. (C) I_DS-V_G curves of FeTFT in erased and programmed states. Threshold voltage V_th is extracted using the linear extrapolation. A memory window is the difference between erased and programmed V_th of FeTFT. V_th change of FeTFT according to (D) amplitudes and (E) widths of program pulses. In operation with different pulse amplitudes, pulse amplitudes are increased from 3 to 5 V and a width is fixed at 1 μs. In operation with different pulse widths, pulse widths are increased from 100 ns to 1 μs and an amplitude is fixed at 5 V. (F) Endurance characteristics of FeTFT for 10⁸ cycles using positive (5 V, 500 ns) and negative (−7 V, 1 μs) triangular pulses for program and erase operations, respectively.

Fig. 2. Operation characteristics of FeNAND.

(A) Optical image of 4 × 4 FeNAND flash memory array (left) and NAND strings in FeNAND flash memory array including programmed cell (C₂₀) and program-inhibited cell (C₂₁) (right). (B and C) Equivalent circuits of FeNAND flash memory array and erase/program operations. V_P, V_E, V_pass, and V_inhibit stand for program, erase, pass, and inhibit voltages, respectively. (D) I_BL-V_WL curves of C₂₀ memory cell and C₂₁ memory cell after erase and program operations. Program of C₂₁ memory cell is prevented by program-inhibit operation. Program-inhibit pulse with an amplitude of V_inhibit = 2.5 V is used for program-inhibit operation. During program-inhibit operation, the channel potential of C₂₁ memory cell could be boosted to V_inhibit.

Fig. 3. Memory operation of FeNAND.

(A) I_BL-V_WL of 16 memory cells in programmed and erased states. (B) Statistical distribution of readout current I_readout of 16 memory cells in programmed (blue) and erased (red) states. (C) NAND operations: All programmed cells (case 1), one erased and all other programmed cells (case 2), and all erased cells (case 3). (D) I_readout of NAND strings in cases 1, 2, and 3. Only the memory string that has all programmed cells shows the on state; when even one cell is erased, the off state is obtained.

Fig. 4. Nanoscale vertical FeTFT array.

(A) Fabrication process flow for vertical FeTFT array. (B) Optical image of the vertical FeTFT device array. S and D stand for source and drain, respectively. (C) Cross-sectional scanning electron microscope image (false colors) of the vertical FeTFT array. (D) Transfer curve of m-TFT with counterclockwise hysteresis. For characterization, V_G sweep is applied to m-TFT gate electrode, while V_pass = 1 V is applied to unselected gate electrodes. (E) V_th change of m-TFT device according to program pulse amplitudes and widths. (F) Endurance characteristics of m-TFT device for 10⁸ cycles using positive (6 V, 1 μs) and negative (−7 V, 1 μs) triangular pulses for program and erase operations, respectively.

Fig. 5. Device simulation of vertical FeTFT array.

(A) Device structure of simulated vertical FeTFT array. (B) Materials and their thicknesses used for simulation. (C) Magnified image of the vertical FeTFT array. (D) Simulated polarization in HfZrO_x layer at programmed and erased states. For program and erase operations, voltage pulses (5 V, 100 μs) and (−5 V, 100 μs) are applied to the m-TFT gate, respectively. Polarization in the HfZrO_x layer is clearly changed after program and erase operations. (E) Experimental and simulated I_DS-V_G curves of the m-TFT at programmed and erased state.

Fig. 6. Device simulation of 3D FeNAND.

(A) Device structure of simulated 3D FeNAND. A single string containing 16 WLs, ground select line (GSL), and string select line (SSL) is simulated. The 30-nm-thick TiN, 24-nm-thick HfZrO_x, and 10-nm-thick InZnO_x are used as WL, ferroelectric gate insulator, and oxide semiconductor channel, respectively. SiO₂ is used as oxide filler material. The thickness of SiO₂ spacer between adjacent WLs is 30 nm. (B) Simulated polarization in HfZrO_x layer after block-erase and program operations. First, all WLs are erased by block-erase operation. Then, WL₁₁ and WL₁₃ cells are programmed. Last, WL₁₂ cell is programmed. Polarization in HfZrO_x layer is clearly changed after block-erase and program operations. (C) Polarization change after block-erase and program operations. a.u., arbitrary units. (D) I_BL-V_WL curves in WL₁₂ cell after block-erase and program operations.