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. 2021 Feb 17;21(4):1392.
doi: 10.3390/s21041392.

Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial

Óscar Ruano  1 , Francisco García-Herrero  1 , Luis Alberto Aranda  1 , Alfonso Sánchez-Macián  1 , Laura Rodriguez  1 , Juan Antonio Maestro  1
Affiliations

Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial

Óscar Ruano et al. Sensors (Basel). .

Abstract

Communication systems that work in jeopardized environments such as space are affected by soft errors that can cause malfunctions in the behavior of the circuits such as, for example, single event upsets (SEUs) or multiple bit upsets (MBUs). In order to avoid this erroneous functioning, this kind of systems are usually protected using redundant logic such as triple modular redundancy (TMR) or error correction codes (ECCs). After the implementation of the protected modules, the communication modules must be tested to assess the achieved reliability. These tests could be driven into accelerator facilities through ionization processes or they can be performed using fault injection tools based on software simulation such as the SEUs simulation tool (SST), or based on field-programmable gate array (FPGA) emulation like the one described in this work. In this paper, a tutorial for the setup of a fault injection emulation platform based on the Xilinx soft error mitigation (SEM) intellectual property (IP) controller is depicted step by step, showing a complete cycle. To illustrate this procedure, an online repository with a complete project and a step-by-step guide is provided, using as device under test a classical communication component such as a finite impulse response (FIR) filter. Finally, the integration of the automatic configuration memory error-injection (ACME) tool to speed up the fault injection process is explained in detail at the end of the paper.

Keywords: FIR filter; SEM IP; SEU; Xilinx; communication modules; emulation; fault injection debugger.

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Conflict of interest statement

The authors declare no conflict of interest.

Figures

Figure 1
Figure 1
Basic components of a receiver.
Figure 2
Figure 2
Operation mode in presence of an SEU (right) and without SEU (left).
Figure 3
Figure 3
(a) Receiver’s Magnitude in presence of a SEU and (b) Receiver’s Phase presence in of a SEU.
Figure 4
Figure 4
Basic components of an error injection environment.
Figure 5
Figure 5
Xilinx FPGA conceptual layers: Application and Configuration layers, extracted from [41].
Figure 6
Figure 6
SEM IP entity.
Figure 7
Figure 7
Design for the experimental setup.
Figure 8
Figure 8
UART model.
Figure 9
Figure 9
Source files overview.
Figure 10
Figure 10
(a) Simulation without an SEU. (b) Simulation with an SEU.
Figure 11
Figure 11
Generation of the SEM IP files through IP example.
Figure 12
Figure 12
SEM example supported by Xilinx.
Figure 13
Figure 13
Original SEM IP constraint file.
Figure 14
Figure 14
Pmod connectors. Front view.
Figure 15
Figure 15
Constraint file example.
Figure 16
Figure 16
Program SRAM configuration memory.
Figure 17
Figure 17
Device programmed with SEM IP observation mode (H17 led).
Figure 18
Figure 18
Jumper for SPI Quad mode Flash programming mode.
Figure 19
Figure 19
Flash memory device for Nexys 4 DDR.
Figure 20
Figure 20
File generation for flash memory (.bin).
Figure 21
Figure 21
Flash memory load.
Figure 22
Figure 22
SEM IP Controller initialized. Ready to receive commands for the injection process.
Figure 23
Figure 23
SEM IP state diagram.
Figure 24
Figure 24
Integration of the ACME tool into fault injection process.
Figure 25
Figure 25
Interface ACME tool.
Figure 26
Figure 26
Example of fault injection loop in MatLab.
See this image and copyright information in PMC

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